Patent US4498136A successfully refreshed from Google Patents.
US4498136A
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Interrupt processor
Assignee: International Business Machines Corp
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Filing: 1982-12-15
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Granted: 1985-02-05
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Expires: 2002-12-15
Abstract
Abstract An interrupt processor is disclosed for an instruction pipelined digital processor, which includes an instruction classification system with a logic class decoder, a multistage, pipelined, interruptible-sequence detector, a multistage variable-return-address generator, and an active instruction completion, suppression, and termination control, to enable interrupting a sequence of instructions which execute out-of-order in the pipelined and digital processor, and to enable allowing a subsequent return to the interrupted program to resume processing of that program without error.
Inventors
- 👤 William W. Sproul, III
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 14:36
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861; G06F9/3865; G06F9/3863
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
214 words
In a data processor, an interrupt processor instruction pipeline having a sequence of instruction stages which sequentially process a machine instruction in respective sequential machine cycles, output from an instruction store, comprising: an interrupt class decoder having an input connected to the output of said instruction store, for decoding each said machine instruction into an interrupt class and outputting a signal on a corresponding one of a plurality of interrupt class output lines; an interrupt sequence detector pipeline having a sequence of staging registers which are connected to said interrupt class output lines and which are sequentially gated in synchronism with said instruction stages of said instruction pipeline, for sequentially propagating a non-interruptible sequence indicator bit to an output line; a register having a data input connected to an interrupt signal line, a control input connected to said output of said interruptible sequence detector pipeline and an output connected to said instruction pipeline, for storing an interrupt signal when said noninterruptible sequence detector bit is input to said control input thereof, said interrupt signal being passed to said instruction pipeline when said detector bit is absent from said control input; whereby interruptions of said instruction pipeline can be selectively inhibited in response to said interrupt classes of said machine instructions in said instruction pipeline.
Claim 2
Dependent Claim
214 words
In a data processor, an interrupt processor instruction pipeline having a sequence of instruction stages which sequentially process a machine instruction in respective sequential machine cycles, output from an instruction store, comprising: an interrupt class decoder having an input connected to the output of said instruction store, for decoding each said machine instruction into an interrupt class and outputting a signal on a corresponding one of a plurality of interrupt class output lines; an interrupt sequence detector pipeline having a sequence of staging registers which are connected to said interrupt class output lines and which are sequentially gated in synchronism with said instruction stages of said instruction pipeline, for sequentially propagating a non-interruptible sequence indicator bit to an output line; a register having a data input connected to an interrupt signal line, a control input connected to said output of said interruptible sequence detector pipeline and an output connected to said instruction pipeline, for storing an interrupt signal when said noninterruptible sequence detector bit is input to said control input thereof, said interrupt signal being passed to said instruction pipeline when said detector bit is absent from said control input; whereby interruptions of said instruction pipeline can be selectively inhibited in response to said interrupt classes of said machine instructions in said instruction pipeline.
Claim 3
Dependent Claim
107 words
The apparatus of claim 1, which further comprises: a return address generator pipeline having a sequence of staging registers which are connected to said interrupt class output lines and which are sequentially gated in synchronism with said instruction stages of said instruction pipeline, for sequentially propagating a program counter indicator to an output line; a program counter storage means having an input connected to said output of said return address generator pipeline, for storing a program counter value in response to said program counter indicator input thereto, for storing the program counter to which said instruction pipeline is to return after an interrupt operation has been completed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-02-05 | 1988-08-06 | 1989-02-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-02-05 | 1992-08-06 | 1993-02-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-02-05 | 1996-08-06 | 1997-02-05 | $7700.00 | Window Closed / Lapsed |