Encoding and decoding systems for binary data

Claim 2

A binary data encoding system comprising: a data input for receiving serial binary data to be encoded; a clock input for receiving a digital clock signal; a reset signal input for receiving a reset signal; a serial to parallel shift register having a data input connected to said binary input and having eight outputs which are designated Q 0 -Q 7 ; a read only memory having eight inputs which are designated A 0 -A 7 and which are aperatively respectively connected to said eight outputs of said serial to parallel shift register and having four outputs which are designated D 0 -D 3 , wherein said read only memory has the following characteristics: ______________________________________ Input Address Output Pattern A.sub.0 A.sub.1 A.sub.2 A.sub.3 A.sub.4 A.sub.5 A.sub.6 A.sub.7 D.sub.0 D.sub.1 D.sub.2 D.sub.3 ______________________________________ 1 1 1 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 1 1 0 Z 1 0 0 1 0 0 1 0 Z 1 0 0 1 0 1 1 0 Z 0 0 0 1 1 0 1 0 R 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 1 0 0 Addresses Except for the Foregoing 0 0 0 0 ______________________________________ wherein Z: all addresses A 4 to A 7 satisfying the inequalities: "A 4 A 5 "≠"00" and "A 4 A 5 A 6 A 7 "≠"1000" R: all addresses A 4 to A 7 satisfying the inequality: "A 4 A 5 A 6 A 7 "≠"1000" and portions with the diagonal lines can have any value; a parallel to serial shift register having four inputs which are designated E-H and which are respectively operatively connected to said four outputs of said read only memory and having an output comprising an output of said binary data encoding system and having a shift clock input operatively connected to said clock input; a first frequency divider having its input connected to said clock input and having its output connected to a shift clock input of said serial to parallel shift register and having a reset input connected to said reset input, said first frequency divider dividing the frequency of said digital clock signal by a factor of two; a second frequency divider whose input is operatively connected to said output of said first frequency divider and whose output is connected to a shift/latch input of said parallel to serial shift register and having a reset input operatively connected to said reset input of said system, said second frequency divider dividing the frequency of a signal input thereto by a factor of two.

Claim 3

A binary data encoding system comprising: a data input for receiving serial binary data to be encoded; a clock input for receiving a digital clock signal; a reset signal input for receiving a reset signal; a serial to parallel shift register having a data input connected to said binary input and having ten outputs which are designated Q 0 -Q 9 ; a read only memory having eight inputs which are designated A 0 -A 7 and which are operatively connected to said ten outputs of said serial to parallel shift register and having four outputs which are designated D 0 -D 3 , wherein said outputs Q 2 -Q 7 are respectively directly connected to inputs A 1 -A 6 and said outputs Q 8 and Q 9 are connected to said input A 7 via an OR gate and said output Q 1 is inverted by a NOT gate and combined with said output Q 0 in an AND gate and input to said input A 0 , and wherein said read only memory has the following characteristics: __________________________________________________________________________ Output Input Address Pattern Conditions for No. A.sub.0 A.sub.1 A.sub.2 A.sub.3 A.sub.4 A.sub.5 A.sub.6 A.sub.7 D.sub.0 D.sub.1 D.sub.2 D.sub.3 Input Address __________________________________________________________________________ 1 1 1 1 1 1 0 0 0 2 0 0 1 1 1 0 0 0 3 0 1 1 1 0 0 0 0 4 1 0 1 1 0 0 0 0 5 0 1 0 0 1 0 6 1 0 1 0 0 0 0 1 0 0 Except Address "A.sub.1 A.sub.2 " = "10" 7 1 0 1 0 0 0 0 0 0 1 8 1 0 1 0 1 0 0 0 0 0 0 9 1 0 1 0 1 0 0 0 1 0 0 Except Address "A.sub.1 A.sub.2 " = "10" 10 1 1 1 0 1 0 0 1 Except Addresses shown by Nos. 6 to 9 11 0 0 1 0 1 0 0 1 Except Addresses shown by Nos. 6 to 9 12 0 1 1 0 0 0 0 1 Except Addresses shown by Nos. 6 to 9 13 1 0 1 0 0 0 0 1 Except Addresses shown by Nos. 6 to 9 14 0 1 0 0 0 0 1 0 0 0 0 Except Address "A.sub.5 A.sub.6 " = "01" 15 0 1 0 0 0 0 1 0 0 0 1 16 1 1 0 0 0 0 0 0 0 17 0 0 0 1 0 0 Except Addresses shown by Nos. - 14 to 16 18 The Foregoing Excepted 0 0 0 0 __________________________________________________________________________ where A 0 =Q 0 ×Q 1 , A 1 =Q 2 , A 2 =Q 3 , A 3 =Q 4 , A 4 =Q 5 , A 5 =Q 6 , A 6 =Q 7 and A 7 =Q 8 +Q 9 portions with diagonal lines can have any logic value; a parallel to serial shift register having four inputs which are designated E-H and which are respectively operatively connected to said four outputs of said read only memory and having an output comprising an output of said binary data encoding system and having a shift clock input operatively connected to said clock input; a first frequency divider having its input connected to said clock input and having its output connected to a shift clock input of said serial to parallel shift register and having a reset input connected to said reset input, said first frequency divider dividing the frequency of said digital clock signal by a factor of two; a second frequency divider whose input is operatively connected to said output of said first frequency divider and whose output is connected to a shift/latch input of said parallel to serial shift register and having a reset input operatively connected to said reset input of said system, said second frequency divider dividing the frequency of a signal input thereto by a factor of two.

Claim 4

A binary data encoding system comprising: a data input for receiving serial binary data to be encoded; a clock input for receiving a digital clock signal; a reset signal input for receiving a reset signal; a serial to parallel shift register having a data input connected to said binary input and having ten outputs which are designated Q 0 -Q 9 ; a read only memory having eight inputs which are designated A 0 -A 7 and which are operatively connected to said ten outputs of said serial to parallel shift register and having four outputs which are designated D 0 -D 3 , wherein said outputs Q 2 -Q 7 are respectively directly connected to inputs A 1 -A 6 and said outputs Q 8 and Q 9 are connected to said input A 7 via an OR gate and said output Q 1 is inverted by a NOT gate and combined with said output Q 0 in an AND gate and input to said input A 0 , and wherein said read only memory has the following characteristics: __________________________________________________________________________ Output Input Address Pattern Conditions for No. A.sub.0 A.sub.1 A.sub.2 A.sub.3 A.sub.4 A.sub.5 A.sub.6 A.sub.7 D.sub.0 D.sub.1 D.sub.2 D.sub.3 Input Address __________________________________________________________________________ 1 1 1 1 1 1 0 0 0 2 0 0 1 1 1 0 0 0 3 0 1 1 1 0 0 0 0 4 1 0 1 1 0 0 0 0 5 0 1 0 0 1 0 6 1 0 1 0 0 0 0 1 0 0 Except Address "A.sub.1 A.sub.2 " = "10" 7 1 0 1 0 0 0 0 0 0 1 8 1 0 1 0 1 0 0 0 0 0 0 9 1 0 1 0 1 0 0 0 1 0 0 Except Address "A.sub.1 A.sub.2 " = "10" 10 1 1 1 0 1 0 0 1 Except Addresses shown by Nos. 6 to 9 11 0 0 1 0 1 0 0 1 Except Addresses shown by Nos. 6 to 9 12 0 1 1 0 0 0 0 1 Except Addresses shown by Nos. 6 to 9 13 1 0 1 0 0 0 0 1 Except Addresses shown by Nos. 6 to 9 14 0 1 0 0 0 0 1 0 0 0 0 Except Address "A.sub.5 A.sub.6 " = "01" 15 0 1 0 0 0 0 1 0 0 0 1 16 1 1 0 0 0 0 0 0 0 17 0 0 0 1 0 0 Except Addresses shown by Nos. - 14 to 16 18 The Foregoing Excepted 0 0 0 0 __________________________________________________________________________ where A 0 =Q 0 ×Q 1 , A 1 =Q 2 , A 2 =Q 3 , A 3 =Q 4 , A 4 =Q 5 , A 5 =Q 6 , A 6 =Q 7 and A 7 =Q 8 +Q 9 portions with diagonal lines can have any logic value; a parallel to serial shift register having four inputs which are designated E-H and which are respectively operatively connected to said four outputs of said read only memory and having an output comprising an output of said binary data encoding system and having a shift clock input operatively connected to said clock input; a first frequency divider having its input connected to said clock input and having its output connected to a shift clock input of said serial to parallel shift register and having a reset input connected to said reset input, said first frequency divider dividing the frequency of said digital clock signal by a factor of two; a second frequency divider whose input is operatively connected to said output of said first frequency divider and whose output is connected to a shift/latch input of said parallel to serial shift register and having a reset input operatively connected to said reset input of said system, said second frequency divider dividing the frequency of a signal input thereto by a factor of two.

Claim 5

A binary data encoding system comprising: a data input for receiving serial binary data to be encoded; a clock input for receiving a digital clock signal; a reset signal input for receiving a reset signal; a serial to parallel shift register having a data input connected to said binary input and having a shift clock input connected to said clock input and having thirteen outputs which are designated Q 0 -Q 12 ; a read only memory having eight inputs which are designated A 0 -A 7 and which are operatively connected to said thirteen outputs of said serial to parallel shift register and having two outputs which are designated D 0 -D 1 , wherein said outputs Q 4 -Q 9 are respectively directly connected to inputs A 1 -A 6 and said outputs Q 10 -Q 12 are connected to said input A 7 via a first OR gate and said outputs Q 0 -Q 3 are connected to said input A 0 via a said OR gate, and wherein said read only memory has the following characteristics: ______________________________________ Output Input Address Pattern A.sub.0 A.sub.1 A.sub.2 A.sub.3 A.sub.4 A.sub.5 A.sub.6 A.sub.7 D.sub.0 D.sub.1 ______________________________________ 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 1 1 Addresses Except for the Foregoing 0 0 ______________________________________ a parallel to serial shift register having two inputs which are designated G-H and which are respectively operatively connected to said outputs D 1 and D 0 of said read only memory and having an output comprising an output of said binary data encoding system and having a shift clock input operatively connected to an output of a first frequency divide; said first frequency divided have its input connected to said clock input and having its output comprising another output of said binary data encoding system and being connected to an input of a second frequency divider and having a reset input connected to said reset input, said first frequency divider dividing the frequency of said digital clock signal by a factor of two; said second frequency divider having an output connected to a shift/latch input of said parallel to serial shift register and having a reset input operatively connected to said reset input of said system, said second frequency divider dividing the frequency of a signal input thereof by a factor of two.

Claim 6

A binary data encoding system comprising: a data input for receiving serial binary data to be encoded; a clock input for receiving a digital clock signal; a reset signal input for receiving a reset signal; a serial to parallel shift register having a data input connected to said binary input and having a shift clock input connected to said clock input and having thirteen outputs which are designated Q 0 -Q 12 ; a read only memory having eight inputs which are designated A 0 -A 7 and which are operatively connected to said thirteen outputs of said serial to parallel shift register and having two outputs which are designated D 0 -D 1 , wherein said outputs Q 4 -Q 9 are respectively directly connected to inputs A 1 -A 6 and said outputs Q 10 -Q 12 are connected to said input A 7 via a first OR gate and said outputs Q 0 -Q 3 are connected to said input A 0 via a said OR gate, and wherein said read only memory has the following characteristics: ______________________________________ Output Input Address Pattern A.sub.0 A.sub.1 A.sub.2 A.sub.3 A.sub.4 A.sub.5 A.sub.6 A.sub.7 D.sub.0 D.sub.1 ______________________________________ 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 1 1 Addresses Except for the Foregoing 0 0 ______________________________________ a parallel to serial shift register having two inputs which are designated G-H and which are respectively operatively connected to said outputs D 1 and D 0 of said read only memory and having an output comprising an output of said binary data encoding system and having a shift clock input operatively connected to an output of a first frequency divide; said first frequency divided have its input connected to said clock input and having its output comprising another output of said binary data encoding system and being connected to an input of a second frequency divider and having a reset input connected to said reset input, said first frequency divider dividing the frequency of said digital clock signal by a factor of two; said second frequency divider having an output connected to a shift/latch input of said parallel to serial shift register and having a reset input operatively connected to said reset input of said system, said second frequency divider dividing the frequency of a signal input thereof by a factor of two.

Claim 7

A binary data encoding system for converting an original two bit data sequence to a converted four bit code comprising: a means for converting a serial data input containing a means for converting a serial data input containing said original data sequence to a parallel form; a converter means operatively connected to said serial to parallel means for converting a parallel output of said serial to parallel converter means to a different parallel form; and a parallel to serial converter means operatively connected to said converter means for converting a parallel output of said converter means to a serial output containing said converted code; wherein said original data sequence is converted to a converted code in accordance with the following: ______________________________________ Original Converted Data Code Conditions ______________________________________ 11 Y000 01 0010 10 0100 "E.sub.2 E.sub.1 " ≠ "10" and "L.sub.1 L.sub.2 " = "00" 10 0001 "E.sub.2 E.sub.1 " = "10" and "L.sub.1 L.sub.2 " = "00" 10 0000 "E.sub.2 E.sub.1 " = "10", "L.sub.1 L.sub.2 " = "10" and "L.sub.3 L.sub.4 " = "00" 10 0100 "E.sub.2 E.sub.1 " ≠ "10", "L.sub.1 L.sub.2 " = "10" and "L.sub.3 L.sub.4 " = "00" 10 Y001 Except the Foregoing 00 0000 "E.sub.2 E.sub.1 " = "10" 00 0100 Except the Foregoing ______________________________________ where E n : data bits preceding by n-bits, 2-bit data to be converted in original data sequence L n : data bits succeeding by n-bits, 2-bit data to be converted in original data sequence and Y: complement logic of logical sum of two bits immediately before code bit Y in converted code sequence supplimentation; a parallel to serial shift register having two inputs which are designated G-H and which are respectively operatively connected to said outputs D 1 and D 0 of said read only memory and having an output comprising an output of said binary data encoding system and having a shift clock input operatively connected to an output of a first frequency divide; said first frequency divided have its input connected to said clock input and having its output comprising another output of said binary data encoding system and being connected to an input of a second frequency divider and having a reset input connected to said reset input, said first frequency divider dividing the frequency of said digital clock signal by a factor of two; said second frequency divider having an output connected to a shift/latch input of said parallel to serial shift register and having a reset input operatively connected to said reset input of said system, said second frequency divider dividing the frequency of a signal input thereto by a factor of two.

Claim 8

A binary data encoding system for converting an original two bit data sequence to a converted four bit code comprising: a means for converting a serial data input containing a means for converting a serial data input containing said original data sequence to a parallel form; a converter means operatively connected to said serial to parallel means for converting a parallel output of said serial to parallel converter means to a different parallel form; and a parallel to serial converter means operatively connected to said converter means for converting a parallel output of said converter means to a serial output containing said converted code; wherein said original data sequence is converted to a converted code in accordance with the following: ______________________________________ Original Converted Data Code Conditions ______________________________________ 11 Y000 01 0010 10 0100 "E.sub.2 E.sub.1 " ≠ "10" and "L.sub.1 L.sub.2 " = "00" 10 0001 "E.sub.2 E.sub.1 " = "10" and "L.sub.1 L.sub.2 " = "00" 10 0000 "E.sub.2 E.sub.1 " = "10", "L.sub.1 L.sub.2 " = "10" and "L.sub.3 L.sub.4 " = "00" 10 0100 "E.sub.2 E.sub.1 " ≠ "10", "L.sub.1 L.sub.2 " = "10" and "L.sub.3 L.sub.4 " = "00" 10 Y001 Except the Foregoing 00 0000 "E.sub.2 E.sub.1 " = "10" 00 0100 Except the Foregoing ______________________________________ where E n : data bits preceding by n-bits, 2-bit data to be converted in original data sequence L n : data bits succeeding by n-bits, 2-bit data to be converted in original data sequence and Y: complement logic of logical sum of two bits immediately before code bit Y in converted code sequence supplimentation; a parallel to serial shift register having two inputs which are designated G-H and which are respectively operatively connected to said outputs D 1 and D 0 of said read only memory and having an output comprising an output of said binary data encoding system and having a shift clock input operatively connected to an output of a first frequency divide; said first frequency divided have its input connected to said clock input and having its output comprising another output of said binary data encoding system and being connected to an input of a second frequency divider and having a reset input connected to said reset input, said first frequency divider dividing the frequency of said digital clock signal by a factor of two; said second frequency divider having an output connected to a shift/latch input of said parallel to serial shift register and having a reset input operatively connected to said reset input of said system, said second frequency divider dividing the frequency of a signal input thereto by a factor of two.

Claim 9

A binary data encoding system for converting an original two bit data sequence to a converted four bit code comprising: a means for converting a serial data input containing said original data sequence to a parallel form; a converter means operatively connected to said serial to parallel means for converting a parallel output of said serial to parallel converter means to a different parallel form; and a parallel to serial converter means operatively connected to said converter means for converting a parallel output of said converter means to a serial output containing said converted code; wherein said original data sequence is converted to a converted code in accordance with the following: ______________________________________ Original Converted Data Code Conditions ______________________________________ 11 Y000 01 0010 10 0100 "E.sub.2 E.sub.1 " ≠ "10" and "L.sub.1 L.sub.2 " = "00" 10 0001 "E.sub.2 E.sub.1 " = "10" and "L.sub.1 L.sub.2 " = "00" 10 0000 "E.sub.2 E.sub.1 " = "10", "L.sub.1 L.sub.2 " = "10" and "L.sub.3 L.sub.4 " = "00" 10 0100 "E.sub.2 E.sub.1 " ≠ "10", "L.sub.1 L.sub.2 " = "10" and "L.sub.3 L.sub.4 " = "00" 10 Y001 Except the Foregoing 00 0000 "E.sub.2 E.sub.1 " = "10" and "E.sub.4 E.sub.3 " ≠ "10" 00 0010 "E.sub.2 E.sub.1 " = " 10" and "E.sub.4 E.sub.3 " = "10" 00 0100 Except the Foregoing ______________________________________ where E n : data bits preceding by n-bits, 2-bit data to be converted in original data sequence L n : data bits succeeding by n-bits, 2-bit data to be converted in original data sequence and Y: complement logic of logical sum of two bits immediately before code bit Y in converted code sequence supplimentation; a parallel to serial shift register having two inputs which are designated G-H and which are respectively operatively connected to said outputs D 1 and D 0 of said read only memory and having an output comprising an output of said binary data encoding system and having a shift clock input operatively connected to an output of a first frequency divide; said first frequency divided have its input connected to said clock input and having its output comprising another output of said binary data encoding system and being connected to an input of a second frequency divider and having a reset input connected to said reset input, said first frequency divider dividing the frequency of said digital clock signal by a factor of two; said second frequency divider having an output connected to a shift/latch input of said parallel to serial shift register and having a reset input operatively connected to said reset input of said system, said second frequency divider dividing the frequency of a signal input thereto by a factor of two.

Claim 10

A binary data encoding system for converting an original two bit data sequence to a converted four bit code comprising: a means for converting a serial data input containing said original data sequence to a parallel form; a converter means operatively connected to said serial to parallel means for converting a parallel output of said serial to parallel converter means to a different parallel form; and a parallel to serial converter means operatively connected to said converter means for converting a parallel output of said converter means to a serial output containing said converted code; wherein said original data sequence is converted to a converted code in accordance with the following: ______________________________________ Original Converted Data Code Conditions ______________________________________ 11 Y000 01 0010 10 0100 "E.sub.2 E.sub.1 " ≠ "10" and "L.sub.1 L.sub.2 " = "00" 10 0001 "E.sub.2 E.sub.1 " = "10" and "L.sub.1 L.sub.2 " = "00" 10 0000 "E.sub.2 E.sub.1 " = "10", "L.sub.1 L.sub.2 " = "10" and "L.sub.3 L.sub.4 " = "00" 10 0100 "E.sub.2 E.sub.1 " ≠ "10", "L.sub.1 L.sub.2 " = "10" and "L.sub.3 L.sub.4 " = "00" 10 Y001 Except the Foregoing 00 0000 "E.sub.2 E.sub.1 " = "10" and "E.sub.4 E.sub.3 " ≠ "10" 00 0010 "E.sub.2 E.sub.1 " = " 10" and "E.sub.4 E.sub.3 " = "10" 00 0100 Except the Foregoing ______________________________________ where E n : data bits preceding by n-bits, 2-bit data to be converted in original data sequence L n : data bits succeeding by n-bits, 2-bit data to be converted in original data sequence and Y: complement logic of logical sum of two bits immediately before code bit Y in converted code sequence supplimentation; a parallel to serial shift register having two inputs which are designated G-H and which are respectively operatively connected to said outputs D 1 and D 0 of said read only memory and having an output comprising an output of said binary data encoding system and having a shift clock input operatively connected to an output of a first frequency divide; said first frequency divided have its input connected to said clock input and having its output comprising another output of said binary data encoding system and being connected to an input of a second frequency divider and having a reset input connected to said reset input, said first frequency divider dividing the frequency of said digital clock signal by a factor of two; said second frequency divider having an output connected to a shift/latch input of said parallel to serial shift register and having a reset input operatively connected to said reset input of said system, said second frequency divider dividing the frequency of a signal input thereto by a factor of two.

Claim 11

A binary data encoding system for converting an original two bit data sequence to a converted four bit code comprising: a means for converting a serial data input containing said original data sequence to a parallel form; a converter means operatively connected to said serial to parallel means for converting a parallel output of said serial to parallel converter means to a different parallel form; and a parallel to serial converter means operatively connected to said converter means for converting a parallel output of said converter means to a serial output containing said converted code; wherein said original data sequence is converted to a converted code in accordance with the following: ______________________________________ Original Converted Data Code Conditions ______________________________________ 11 Y000 01 0010 10 0100 "E.sub.2 E.sub.1 " ≠ "10" and "L.sub.1 L.sub.2 " = "00" 10 0001 "E.sub.2 E.sub.1 " = "10" and "L.sub.1 L.sub.2 " = "00" 10 0000 "E.sub.2 E.sub.1 " = "10", "L.sub.1 L.sub.2 " = "10" and "L.sub.3 L.sub.4 " = "00" 10 0100 "E.sub.2 E.sub.1 " ≠ "10", "L.sub.1 L.sub.2 " = "10" and "L.sub.3 L.sub.4 " = "00" 10 Y001 Except the Foregoing 00 0000 "E.sub.4 E.sub.3 " ≠ "10", "E.sub.2 E.sub.1 " = "10" and "L.sub.1 L.sub.2 " ≠ "01" 00 0001 "E.sub.4 E.sub.3 " ≠ "10", "E.sub.2 E.sub.1 " = "10" and "L.sub.1 L.sub.2 " = "01" 00 0000 "E.sub.2 E.sub.1 " = "10" 00 0100 Except the Foregoing ______________________________________ where E n : data bits preceding by n-bits, 2-bit data to be converted in original data sequence L n : data bits secceeding by n-bits, 2-bit data to be converted in original data sequence and Y: complement logic of logical sum of two bits immediately before code bit Y in converted code sequence supplimentation; a parallel to serial shift register having two inputs which are designated G-H and which are respectively operatively connected to said outputs D 1 and D 0 of said read only memory and having an output comprising an output of said binary data encoding system and having a shift clock input operatively connected to an output of a first frequency divide; said first frequency divided have its input connected to said clock input and having its output comprising another output of said binary data encoding system and being connected to an input of a second frequency divider and having a reset input connected to said reset input, said first frequency divider dividing the frequency of said digital clock signal by a factor of two; said second frequency divider having an output connected to a shift/latch input of said parallel to serial shift register and having a reset input operatively connected to said reset input of said system, said second frequency divider dividing the frequency of a signal input thereto by a factor of two.

Claim 12

A binary data encoding system for converting an original two bit data sequence to a converted four bit code comprising: a means for converting a serial data input containing said original data sequence to a parallel form; a converter means operatively connected to said serial to parallel means for converting a parallel output of said serial to parallel converter means to a different parallel form; and a parallel to serial converter means operatively connected to said converter means for converting a parallel output of said converter means to a serial output containing said converted code; wherein said original data sequence is converted to a converted code in accordance with the following: ______________________________________ Original Converted Data Code Conditions ______________________________________ 11 Y000 01 0010 10 0100 "E.sub.2 E.sub.1 " ≠ "10" and "L.sub.1 L.sub.2 " = "00" 10 0001 "E.sub.2 E.sub.1 " = "10" and "L.sub.1 L.sub.2 " = "00" 10 0000 "E.sub.2 E.sub.1 " = "10", "L.sub.1 L.sub.2 " = "10" and "L.sub.3 L.sub.4 " = "00" 10 0100 "E.sub.2 E.sub.1 " ≠ "10", "L.sub.1 L.sub.2 " = "10" and "L.sub.3 L.sub.4 " = "00" 10 Y001 Except the Foregoing 00 0000 "E.sub.4 E.sub.3 " ≠ "10", "E.sub.2 E.sub.1 " = "10" and "L.sub.1 L.sub.2 " ≠ "01" 00 0001 "E.sub.4 E.sub.3 " ≠ "10", "E.sub.2 E.sub.1 " = "10" and "L.sub.1 L.sub.2 " = "01" 00 0000 "E.sub.2 E.sub.1 " = "10" 00 0100 Except the Foregoing ______________________________________ where E n : data bits preceding by n-bits, 2-bit data to be converted in original data sequence L n : data bits secceeding by n-bits, 2-bit data to be converted in original data sequence and Y: complement logic of logical sum of two bits immediately before code bit Y in converted code sequence supplimentation; a parallel to serial shift register having two inputs which are designated G-H and which are respectively operatively connected to said outputs D 1 and D 0 of said read only memory and having an output comprising an output of said binary data encoding system and having a shift clock input operatively connected to an output of a first frequency divide; said first frequency divided have its input connected to said clock input and having its output comprising another output of said binary data encoding system and being connected to an input of a second frequency divider and having a reset input connected to said reset input, said first frequency divider dividing the frequency of said digital clock signal by a factor of two; said second frequency divider having an output connected to a shift/latch input of said parallel to serial shift register and having a reset input operatively connected to said reset input of said system, said second frequency divider dividing the frequency of a signal input thereto by a factor of two.

Claim 13

A binary data encoding system for converting an original two bit data sequence to a converted four bit code comprising: a means for converting a serial data input containing said original data sequence to a parallel form; a converter means operatively connected to said serial to parallel means for converting a parallel output of said serial to parallel converter means to a different parallel form; and a parallel to serial converter means operatively connected to said converter means for converting a parallel output of said converter means to a serial output containing said converted code; wherein said original data sequence is converted to a converted code in accordance with the following: ______________________________________ Original Converted Data Code Conditions ______________________________________ 11 Y000 01 0000 "E.sub.6 E.sub.5 " ≠ "10", "E.sub.4 E.sub.3 " = "10" and "E.sub.2 E.sub.1 " = "00" 01 0010 Except the Foregoing 10 0100 "E.sub.2 E.sub.1 " ≠ "10" and "L.sub.1 L.sub.2 " = "00" 10 0001 "E.sub.2 E.sub.1 " = "10" and "L.sub.1 L.sub.2 " = "00" 10 0000 "E.sub.2 E.sub.1 " = "10", "L.sub.1 L.sub.2 " = "10" and "L.sub.3 L.sub.4 = "00" 10 0100 "E.sub.2 E.sub.1 " ≠ "10", "L.sub.1 L.sub.2 " = "10" and "L.sub.3 L.sub.4 " = "00" 10 Y001 Except the Foregoing 00 0000 "E.sub.4 E.sub.3 " ≠ "10", "E.sub.2 E.sub.1 " = "10" and "L.sub.1 L.sub.2 " ≠ "01" 00 0001 "E.sub.4 E.sub.3 " ≠ "10", "E.sub.2 E.sub.1 " = "10" and "L.sub.1 L.sub.2 " = "01" 00 0010 "E.sub.4 E.sub.3 " = "10" and "E.sub.2 E.sub.1 " = 10 00 0100 Except the Foregoing ______________________________________ where E n : data bits preceding by n-bits, 2-bit data to be converted in original data sequence L n : data bits secceeding by n-bits, 2-bit data to be converted in original data sequence and Y: complement logic of logical sum of two bits immediately before code bit Y in converted code sequence supplimentation; a parallel to serial shift register having two inputs which are designated G-H and which are respectively operatively connected to said outputs D 1 and D 0 of said read only memory and having an output comprising an output of said binary data encoding system and having a shift clock input operatively connected to an output of a first frequency divide; said first frequency divided have its input connected to said clock input and having its output comprising another output of said binary data encoding system and being connected to an input of a second frequency divider and having a reset input connected to said reset input, said first frequency divider dividing the frequency of said digital clock signal by a factor of two; said second frequency divider having an output connected to a shift/latch input of said parallel to serial shift register and having a reset input operatively connected to said reset input of said system, said second frequency divider dividing the frequency of a signal input thereto by a factor of two.

Claim 14

A binary data encoding system for converting an original two bit data sequence to a converted four bit code comprising: a means for converting a serial data input containing said original data sequence to a parallel form; a converter means operatively connected to said serial to parallel means for converting a parallel output of said serial to parallel converter means to a different parallel form; and a parallel to serial converter means operatively connected to said converter means for converting a parallel output of said converter means to a serial output containing said converted code; wherein said original data sequence is converted to a converted code in accordance with the following: ______________________________________ Original Converted Data Code Conditions ______________________________________ 11 Y000 01 0000 "E.sub.6 E.sub.5 " ≠ "10", "E.sub.4 E.sub.3 " = "10" and "E.sub.2 E.sub.1 " = "00" 01 0010 Except the Foregoing 10 0100 "E.sub.2 E.sub.1 " ≠ "10" and "L.sub.1 L.sub.2 " = "00" 10 0001 "E.sub.2 E.sub.1 " = "10" and "L.sub.1 L.sub.2 " = "00" 10 0000 "E.sub.2 E.sub.1 " = "10", "L.sub.1 L.sub.2 " = "10" and "L.sub.3 L.sub.4 = "00" 10 0100 "E.sub.2 E.sub.1 " ≠ "10", "L.sub.1 L.sub.2 " = "10" and "L.sub.3 L.sub.4 " = "00" 10 Y001 Except the Foregoing 00 0000 "E.sub.4 E.sub.3 " ≠ "10", "E.sub.2 E.sub.1 " = "10" and "L.sub.1 L.sub.2 " ≠ "01" 00 0001 "E.sub.4 E.sub.3 " ≠ "10", "E.sub.2 E.sub.1 " = "10" and "L.sub.1 L.sub.2 " = "01" 00 0010 "E.sub.4 E.sub.3 " = "10" and "E.sub.2 E.sub.1 " = 10 00 0100 Except the Foregoing ______________________________________ where E n : data bits preceding by n-bits, 2-bit data to be converted in original data sequence L n : data bits secceeding by n-bits, 2-bit data to be converted in original data sequence and Y: complement logic of logical sum of two bits immediately before code bit Y in converted code sequence supplimentation; a parallel to serial shift register having two inputs which are designated G-H and which are respectively operatively connected to said outputs D 1 and D 0 of said read only memory and having an output comprising an output of said binary data encoding system and having a shift clock input operatively connected to an output of a first frequency divide; said first frequency divided have its input connected to said clock input and having its output comprising another output of said binary data encoding system and being connected to an input of a second frequency divider and having a reset input connected to said reset input, said first frequency divider dividing the frequency of said digital clock signal by a factor of two; said second frequency divider having an output connected to a shift/latch input of said parallel to serial shift register and having a reset input operatively connected to said reset input of said system, said second frequency divider dividing the frequency of a signal input thereto by a factor of two.