Method of making high density semiconductor device such as floating gate electrically programmable ROM or the like

Claim 2

A floating gate type semiconductor memory array comprising: a plurality of MOS transistor devices each having a source, a drain, a floating gate, and a control gate, the floating gate being isolated from the channel between source and drain by thin insulator and the control gate being isolated from the floating gate by thin insulator, the transistor devices being arranged in an array of rows and columns, with the columns of transistor devices being separated by elongated parallel heavily-doped regions in the semiconductor which define column lines; means connecting the control gates of all device in each row together to provide row lines; said elongated parallel heavily-doped semiconductor regions forming the source and drain regions of the transistor devices as well as connecting the sources and drains of all adjacent devices together to provide said column lines, one pair of opposite parallel edges of the floating gate in each transistor device being aligned with edges of the control gates of all transistor devices in each row, and the other pair of opposite parallel edges of the floating gate in each transistor device being aligned with edges of the elongated parallel heavily-doped regions.

Claim 3

A memory array according to claim 1 wherein the transistor devices are N-channel and the floating gate and control gate are separate layers of polycrystalline silicon.

Claim 4

A memory array according to claim 1 wherein said elongated parallel heavily-doped regions underlie thick field oxide penetrating into said face.

Claim 5

A memory array according to claim 3 wherein the thick field oxide is thermally grown silicon oxide in parallel strips between the columns of transistor devices.

Claim 6

A memory array according to claim 3 wherein the thick field oxide is aligned with said other pair of opposite parallel edges of the floating gates of the transistor devices.

Claim 7

A semiconductor memory array formed in a face of a semiconductor body comprising: a plurality of MOS transistor devices, each transistor device having a source-to-drain path and a gate, the gate being isolated from the source-to-drain path by thin insulator; a plurality of MOS capacitor devices, one for each transistor device, each capacitor device having an upper electrode isolated from a surface region by thin insulator; the transistor devices and capacitor devices being arranged in an array of rows and columns; a plurality of elongated parallel heavily-doped regions in the face which define column lines; means connecting said gates of all devices in each row together to provide row lines; each of said elongated parallel heavily-doped semiconductor regions forming one end of the source-to-drain paths of the transistor devices as well as connecting said one end of all transistor devices in a column together to provide said column lines, one pair of opposite parallel edges of the gate in each transistor device being aligned with edges of the source-to-drain path of such transistor device, and the other pair of opposite parallel edges of the gate in each transistor device being aligned with an edge of one of the elongated parallel heavily-doped regions one one side and the upper electrode of the associated capacitor device on the other side.

Claim 8

A semiconductor memory array formed in a face of a semiconductor body comprising: a plurality of MOS transistor devices, each transistor device having a source-to-drain path and a gate, the gate being isolated from the source-to-drain path by thin insulator; a plurality of MOS capacitor devices, one for each transistor device, each capacitor device having an upper electrode isolated from a surface region by thin insulator; the transistor devices and capacitor devices being arranged in an array of rows and columns; a plurality of elongated parallel heavily-doped regions in the face which define column lines; means connecting said gates of all devices in each row together to provide row lines; each of said elongated parallel heavily-doped semiconductor regions forming one end of the source-to-drain paths of the transistor devices as well as connecting said one end of all transistor devices in a column together to provide said column lines, one pair of opposite parallel edges of the gate in each transistor device being aligned with edges of the source-to-drain path of such transistor device, and the other pair of opposite parallel edges of the gate in each transistor device being aligned with an edge of one of the elongated parallel heavily-doped regions one one side and the upper electrode of the associated capacitor device on the other side.

Claim 9

A memory array according to claim 6 wherein the transistor devices are N-channel and the upper electrode and gate are separate layers of polycrystalline silicon.

Claim 10

A memory array according to claim 1, wherein said elongated parallel heavily-doped regions underlie thick field oxide penetrating into said face.

Claim 11

A memory array according to claim 8 wherein the thick field oxide is thermally grown silicon oxide in parallel strips wider than the heavily-doped regions.

Claim 12

A memory array according to claim 9 wherein the thick field oxide is aligned on one side with said upper electrodes which define elongated strips perpendicular to the row lines.

Claim 13

A memory device comprising an array of rows and columns of dynamic memory cells in a face of a semiconductor body of one conductivity type, each cell having a transistor with a source-to-drain path in said face and a gate overlying said face, the source-to-drain path including a region of opposite conductivity type in said face, each cell having a capacitor with a capacitor region in said face and a capacitor plate overlying the capacitor region separated therefrom by an insulator of a given thickness, the capacitor plate for a plurality of the cells being part of a continuous layer of conductive material extending along said face, a given one of the capacitor regions being isolated along the face from an adjacent capacitor region by a doped surface region in the face beneath the layer composed of semiconductor material of said one conductivity type of concentration much greater than that immediately underlying such surface region and differing from that of the capacitor region, the layer being separated from said surface region by an insulator of about said given thickness.

Claim 14

A memory device comprising an array of rows and columns of dynamic memory cells in a face of a semiconductor body of one conductivity type, each cell having a transistor with a source-to-drain path in said face and a gate overlying said face, the source-to-drain path including a region of opposite conductivity type in said face, each cell having a capacitor with a capacitor region in said face and a capacitor plate overlying the capacitor region separated therefrom by an insulator of a given thickness, the capacitor plate for a plurality of the cells being part of a continuous layer of conductive material extending along said face, a given one of the capacitor regions being isolated along the face from an adjacent capacitor region by a doped surface region in the face beneath the layer composed of semiconductor material of said one conductivity type of concentration much greater than that immediately underlying such surface region and differing from that of the capacitor region, the layer being separated from said surface region by an insulator of about said given thickness.

Claim 15

A device according to claim 11 wherein said conductive material is polycrystalline silicon, said semiconductor body is P type silicon, and said surface regon is P+ silicon.

Claim 16

A device according to claim 12 wherein field oxide much thicker than said given thickness and extending into the face functions to isolate at least one side of each capacitor from one of said regions of opposite conductivity.

Claim 17

A device according to claim 11 wherein said doped surface region has a surface in the same plane with surface of said adjacent capacitor region, and said layer extends along the face in a single plane from said one capacitor region to said adjacent capacitor region.