Patent US4490629A successfully refreshed from Google Patents.
US4490629A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High voltage circuits in low voltage CMOS process
Assignee: AMI Semiconductor Inc
•
Filing: 1982-05-10
•
Granted: 1984-12-25
•
Expires: 2002-05-10
Abstract
Abstract A CMOS push-pull output buffer (171) is constructed utilizing a plurality of N channel transistors (74, 75, 76) and a plurality of P channel transistors (71, 72, 73) connected in series. The voltages applied to the gates of the N channel transistors and P channel transistors are selected to divide the high voltage (+V) substantially equally across the P channel transistors, when the P channel transistors are turned off, and substantially evenly divide the high voltage across the N channel transistors, when the N channel transistors are turned off. In another embodiment of this invention, selected ones of the N channel and P channel transistors are formed in order to have a high drain to bulk breakdown voltage. In another embodiment of this invention, a plurality of N channel and a plurality of P channel transistors are connected in series and driven by a single ended control voltage (C N ), thus providing a first stage (101) which drives a second stage (100) having a plurality of P channel transistors and a plurality of N channel transistors (110, 111, 112), which provide the high voltage output voltage. In another embodiment of this invention, the first stage (101) is driven by a single ended control voltage (C N ) and serves to drive a second stage (103) comprising a plurality of N channel transistors (110, 111, 112) and a plurality of bipolar transistors (120, 121), whereby said second stage provides the high voltage output signal.
Inventors
- 👤 Allen R. Barlow
- 👤 Corey Petersen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 12:54
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/998; H03; H03F; H03F3/00; H03F3/42; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H03K19/0948
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
299 words
A complementary metal oxide silicon push-pull output buffer, comprising: an input node; an output node; a plurality of j P channel MOS transistors, where j is an integer greater than one, each of said j P channel MOS transistors having a control gate, the source of the first P channel MOS transistor being connected to a source of positive voltage V, the drain of the ith P channel MOS transistor being connected to the source of the ith+1 P channel MOS transistor, where i is an integer ranging from 1 to (j-1), and the drain of the jth P channel MOS transistor being connected to said output node; a plurality of k N channel MOS transistors, where k is an integer greater than one, each of said k N channel MOS transistors having a control gate, a source and a drain, the source of the first N channel MOS transistor being connected to a reference potential, the drain of the Lth N channel MOS transistor being connected to the source of the Lth+1 N channel MOS transistor, where L is an integer ranging from 1 to (k-1), and the drain of said kth N channel MOS transistor being connected to said output node, wherein a set of voltages are applied to the gates of (j-1) of said P channel MOS transistors and to the gates of k-1 of said N channel MOS transistors so as to prevent a voltage in excess of the breakdown voltage from being established on each of said N channel and P channel MOS transistors when turned off, and wherein the remaining N channel and P channel MOS transistors receive control signals on their gates from said input node, said control signals applied to said input node for controlling the state of said output buffer.
Claim 2
Dependent Claim
299 words
A complementary metal oxide silicon push-pull output buffer, comprising: an input node; an output node; a plurality of j P channel MOS transistors, where j is an integer greater than one, each of said j P channel MOS transistors having a control gate, the source of the first P channel MOS transistor being connected to a source of positive voltage V, the drain of the ith P channel MOS transistor being connected to the source of the ith+1 P channel MOS transistor, where i is an integer ranging from 1 to (j-1), and the drain of the jth P channel MOS transistor being connected to said output node; a plurality of k N channel MOS transistors, where k is an integer greater than one, each of said k N channel MOS transistors having a control gate, a source and a drain, the source of the first N channel MOS transistor being connected to a reference potential, the drain of the Lth N channel MOS transistor being connected to the source of the Lth+1 N channel MOS transistor, where L is an integer ranging from 1 to (k-1), and the drain of said kth N channel MOS transistor being connected to said output node, wherein a set of voltages are applied to the gates of (j-1) of said P channel MOS transistors and to the gates of k-1 of said N channel MOS transistors so as to prevent a voltage in excess of the breakdown voltage from being established on each of said N channel and P channel MOS transistors when turned off, and wherein the remaining N channel and P channel MOS transistors receive control signals on their gates from said input node, said control signals applied to said input node for controlling the state of said output buffer.
Claim 3
Dependent Claim
78 words
Structure as in claim 1 wherein said output buffer has a first state wherein each of said N channel MOS transistors is off and each of said P channel transistors is on, whereby said source of positive voltage is applied to said output node; and a second state, wherein each of said N channel MOS transistors is on and each of said P channel MOS transistors is off, whereby said output node is connected to said reference potential.
Claim 4
Dependent Claim
113 words
Structure as in claim 2 wherein during said first state: said first P channel MOS transistor receives on its gate a first control voltage sufficient to turn said first P channel MOS transistor on and said first N channel MOS transistor receives on its gate a second control voltage sufficient to turn said first N channel transistor off, and wherein during said second state said first P channel MOS transistor receives on its gate a third control voltage sufficient to turn said first P channel MOS transistor off and said first N channel MOS transistor receives on its gate a fourth control voltage sufficient to turn said first N channel MOS transistor on.
Claim 5
Dependent Claim
89 words
Structure as in claim 2 wherein: said first P channel MOS transistor receives on its gate a bias voltage sufficient to turn said first P channel MOS transistor on; and wherein during said first state said first N channel MOS transistor receives on its gate a second control voltage sufficient to turn said first N channel MOS transistor off; and wherein during said second state said first N channel MOS transistor receives on its gate a third control voltage sufficient to turn said first N channel MOS transistor on.
Claim 6
Dependent Claim
66 words
Structure as in claim 3 or 4 wherein a voltage substantially equal to (V(n-1)/k) is applied to the gates of the nth N channel MOS transistor, where n is an integer ranging from 2 to k, and wherein a voltage substantially equal to (V(m-1))j is applied to the gates of the mth P channel MOS transistor, where m is an integer ranging from 2 to j.
Claim 7
Dependent Claim
24 words
Structure as in claim 5 wherein the N type bulk silicon of each said P channel MOS transistor is connected to said positive voltage.
Claim 8
Dependent Claim
23 words
Structure as in claim 5 wherein the P type bulk silicon of each said N channel MOS transistor is connected to its source.
Claim 9
Dependent Claim
23 words
Structure as in claim 5 wherein the N type bulk silicon of each said P channel MOS transistor is connected to its source.
Claim 10
Dependent Claim
65 words
Structure as in claim 5 wherein at least one of said P channel MOS transistors comprises: a region of N- type bulk silicon; a P+ type source region formed in said N- type bulk silicon; a P+ type drain region formed in said N- type bulk silicon; and a P- type region surrounding said P+ type drain region formed in said N- type bulk silicon.
Claim 11
Dependent Claim
65 words
Structure as in claim 5 wherein at least one of said N channel MOS transistors comprises: a region of P- type bulk silicon; an N+ type source region formed in said P- type bulk silicon; an N+ type drain region formed in said P- type bulk silicon; and an N- type region surrounding said N+ type drain region formed in said P- type bulk silicon.
Claim 12
Dependent Claim
242 words
A push-pull output buffer, comprising: an input node; an output node; two bipolar NPN transistors, both of said bipolar NPN transistors having a base, the collectors of said bipolar NPN transistors being commonly connected to a source of positive voltage V, the emitter of the first bipolar NPN transistor being connected to the base of the second bipolar NPN transistor and the emitter of the second bipolar NPN transistor being connected to said output node; a plurality of k N channel MOS transistors, where k is an integer greater than one, each of said N channel MOS transistors having a control gate, a source and a drain, the source of the first N channel MOS transistor being connected to a reference potential, the drain of the Lth N channel MOS transistor being connected to the source of the Lth+1 N channel transistor, where L is an integer ranging from 1 to (k-1), and the drain of said kth N channel MOS transistor being connected to said output node, wherein a set of voltages are applied to the gates of (k-1) of said N channel MOS transistors so as to prevent a voltage in excess of the breakdown voltage from being established on each said N channel MOS transistor; wherein the remaining N channel MOS and said first bipolar NPN transistor receive on their gate and base, respectively, control signals applied to said input node for controlling the state of said output buffer.
Claim 13
Dependent Claim
242 words
A push-pull output buffer, comprising: an input node; an output node; two bipolar NPN transistors, both of said bipolar NPN transistors having a base, the collectors of said bipolar NPN transistors being commonly connected to a source of positive voltage V, the emitter of the first bipolar NPN transistor being connected to the base of the second bipolar NPN transistor and the emitter of the second bipolar NPN transistor being connected to said output node; a plurality of k N channel MOS transistors, where k is an integer greater than one, each of said N channel MOS transistors having a control gate, a source and a drain, the source of the first N channel MOS transistor being connected to a reference potential, the drain of the Lth N channel MOS transistor being connected to the source of the Lth+1 N channel transistor, where L is an integer ranging from 1 to (k-1), and the drain of said kth N channel MOS transistor being connected to said output node, wherein a set of voltages are applied to the gates of (k-1) of said N channel MOS transistors so as to prevent a voltage in excess of the breakdown voltage from being established on each said N channel MOS transistor; wherein the remaining N channel MOS and said first bipolar NPN transistor receive on their gate and base, respectively, control signals applied to said input node for controlling the state of said output buffer.
Claim 14
Dependent Claim
77 words
Structure as in claim 11 wherein said output buffer has a first state wherein each of said N channel MOS transistors is off and each of said bipolar NPN transistors is on, whereby said source of positive voltage is applied to said output node; and a second state, wherein each of said N channel MOS transistors is on and each of said bipolar NPN transistors is off, whereby said output node is connected to said reference potential.
Claim 15
Dependent Claim
109 words
Structure as in claim 12 wherein during said first state: said first bipolar NPN transistor receives on its base a first control voltage sufficient to turn said first bipolar NPN transistor on and said first N channel MOS transistor receives on its gate a second control voltage sufficient to turn said first N channel transistor off, and wherein during said second state said first bipolar NPN transistor receives on its base a third control voltage sufficient to turn said first bipolar NPN transistor off and said first N channel MOS transistor receives on its gate a fourth control voltage sufficient to turn said first N channel MOS transistor on.
Claim 16
Dependent Claim
34 words
Structure ad in claim 13 wherein a voltage substantially equal to (V(n-1))/k is applied to said gate of said nth N channel MOS transistor, where n is an integer ranging from 2 to k.
Claim 17
Dependent Claim
30 words
Structure as in claim 14 further comprising two resistors, both of said resistors connected between the base and the emitter of an associated one of said two bipolar NPN transistors.
Claim 18
Dependent Claim
65 words
Structure as in claim 14 wherein at least one of said N channel MOS transistors comprises: a region of P- type bulk silicon; an N+ type source region formed in said P- type bulk silicon; an N+ type drain region formed in said P- type bulk silicon; and an N- type region surrounding said N+ type drain region formed in said P- type bulk silicon.
Claim 19
Dependent Claim
23 words
Structure as in claim 11 wherein the P type bulk silicon of each said N channel MOS transistor is connected to its source.
References Cited (Backward Citations)
US3991326A
Cited
US4172260A
Cited
US4161663A
Cited
US4317055A
Cited
US4313065A
Cited
US4296335A
Cited
US4429237A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-12-25 | 1988-06-25 | 1988-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-12-25 | 1992-06-25 | 1992-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-12-25 | 1996-06-25 | 1996-12-25 | $7700.00 | Window Closed / Lapsed |