US4488303A — Fail-safe circuit for a microcomputer based system

Claim 1

Independent Claim 209 words

A fail-safe protection circuit for a data processing controlled system having stored programs, a plurality of data output terminals, and a first output terminal and comprising: means for checking the execution of its programs at periodic intervals not greater than T 1 to produce an output trigger pulse on said first output terminal at said periodic intervals if said program execution is correct up to that time, and comprising: a first retriggerable two-state one-shot device responsive to said output pulses to become triggered to its first state and having a time delay T 2 before it changes from its triggered first state to its second state, where T 2 >T 1 ; a plurality of gating means each having a first input terminal connected to an individual one of said data output terminals, a second input terminal coupled to the said first retriggerable two-state, one-shot device, and a second output terminal; and said gating means responsive to the first state of said first retriggerable, two-state, one-shot device to become primed to pass therethough the data supplied to said first input terminal and responsive to the second state of said first retriggerable, two-state, one-shot device to inhibit the passage therethrough of the data supplied to said first input terminal thereof.

Claim 2

Dependent Claim 209 words

A fail-safe protection circuit for a data processing controlled system having stored programs, a plurality of data output terminals, and a first output terminal and comprising: means for checking the execution of its programs at periodic intervals not greater than T 1 to produce an output trigger pulse on said first output terminal at said periodic intervals if said program execution is correct up to that time, and comprising: a first retriggerable two-state one-shot device responsive to said output pulses to become triggered to its first state and having a time delay T 2 before it changes from its triggered first state to its second state, where T 2 >T 1 ; a plurality of gating means each having a first input terminal connected to an individual one of said data output terminals, a second input terminal coupled to the said first retriggerable two-state, one-shot device, and a second output terminal; and said gating means responsive to the first state of said first retriggerable, two-state, one-shot device to become primed to pass therethough the data supplied to said first input terminal and responsive to the second state of said first retriggerable, two-state, one-shot device to inhibit the passage therethrough of the data supplied to said first input terminal thereof.

Claim 3

Dependent Claim 52 words

A circuit as in claim 1 and further comprising: a second retriggerable two-state, one-shot device responsive to the change from the first to the second state of said first retriggerable device to produce a second output signal; said data processing controlled system responsive to said second output signal to re-initiate its operation.

Claim 4

Dependent Claim 48 words

A circuit as in claim 2 in which said data processing controlled system comprises controlled devices and further comprising logic means responsive to the absence of N consecutive output trigger pulses to disable said data processing controlled system and to place said controlled devices in predetermined operating states.

Claim 5

Dependent Claim 51 words

A circuit as in claim 1 and further comprising: a signal generating means responsive to the change from the first to the second state of said first retriggerable device to produce a second output signal; and said data processing controlled system responsive to said second output signal to re-initiate its operation.

Claim 6

Dependent Claim 48 words

A circuit as in claim 4 in which said data processing controlled system comprises controlled devices and further comprising logic means responsive to the absence of N consecutive output trigger pulses to disable said data processing controlled system and to place said controlled devices in predetermined operating states.

Claim 7

Independent Claim 97 words

A method of providing fail-safe protection for a data processor controlled system should it fail comprising the steps of: a. generating a series of periodic trigger pulses during proper operation of the system with the periods between said periodic pulses not exceeding a time interval T 1 ; b. generating a control signal when the trigger pulses cease for a time interval T 2 ; c. blocking the flow of data in said data processing system in response to said control signal; and d. re-initiating operation of said data processing system in response to said control signal.

Claim 8

Independent Claim 97 words

A method of providing fail-safe protection for a data processor controlled system should it fail comprising the steps of: a. generating a series of periodic trigger pulses during proper operation of the system with the periods between said periodic pulses not exceeding a time interval T 1 ; b. generating a control signal when the trigger pulses cease for a time interval T 2 ; c. blocking the flow of data in said data processing system in response to said control signal; and d. re-initiating operation of said data processing system in response to said control signal.

Claim 9

Dependent Claim 45 words

A method as in claim 6 comprising the further steps of: e. disabling said data processor after an absence of N trigger pulses in response to said control signal; and f. placing the data processor controlled system in a predetermined operating state after disablement thereof.

Claim 10

Independent Claim 98 words

A method of providing fail-safe protection for a data processor controlled system should it fail and comprising the steps of: a. generating a series of periodic trigger pulses during proper operation of the system with the periods between said periodic pulses not exceeding a time interval T 1 ; b. interrupting the operation of said data processor controlled system when the trigger pulses cease for a time interval T 2 , where T 2 >T 1 ; and c. re-initiating operation of said data processor after a time interval T 3 following the time interval T 2 .

Claim 11

Independent Claim 98 words

A method of providing fail-safe protection for a data processor controlled system should it fail and comprising the steps of: a. generating a series of periodic trigger pulses during proper operation of the system with the periods between said periodic pulses not exceeding a time interval T 1 ; b. interrupting the operation of said data processor controlled system when the trigger pulses cease for a time interval T 2 , where T 2 >T 1 ; and c. re-initiating operation of said data processor after a time interval T 3 following the time interval T 2 .

Claim 12

Dependent Claim 56 words

A method as in claim 8 comprising the further steps of: d. disabling said data processor controlled system after an absence of N trigger pulses for a time period T 2 and consequent interruption of said data processor controlled system; and e. placing the data processor controlled system in a predetermined operating state after disablement thereof.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1987-12-11	1988-06-11	1988-12-11	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1991-12-11	1992-06-11	1992-12-11	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1995-12-11	1996-06-11	1996-12-11	$7700.00	Window Closed / Lapsed

Fail-safe circuit for a microcomputer based system

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