Patent US4488230A successfully refreshed from Google Patents.
US4488230A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmed logic array with external signals introduced between its AND plane and its OR plane
Assignee: Nokia Bell Labs
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Filing: 1983-06-20
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Granted: 1984-12-11
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Expires: 2003-06-20
Abstract
Abstract A combinational logic device, such as an AND gate, is connected to control the flow of information along a wordline from the AND plane to the OR plane of a PLA (programmed logic array). To each such combinational logic device is applied an input signal from a source external to the PLA, so that the PLA's output can respond relatively quickly to this input signal--that is, the PLA is capable of relatively quick decision making.
Inventors
- 👤 Marc L. Harrison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 19:02
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/223; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17716; H03K19/1772
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
134 words
A PLA comprising an AND plane, an OR plane, and a plurality of intermediate wordlines running from the AND plane to the OR plane, and having at least one transistor for modifying during operation of the PLA a flow of data from the AND to the OR plane along at least one of the wordlines, said one of the wordlines consisting of first and second lines interconnected by the source-drain path of the transistor, an intermediate signal line being connected to an input terminal of the transistor for delivering thereto an input signal from a source external to the PLA, whereby during operation of the PLA when the input signal on the intermediate signal line is a WAIT signal the flow of data along said one of the wordlines is interrupted by the transistor.
Claim 2
Dependent Claim
134 words
A PLA comprising an AND plane, an OR plane, and a plurality of intermediate wordlines running from the AND plane to the OR plane, and having at least one transistor for modifying during operation of the PLA a flow of data from the AND to the OR plane along at least one of the wordlines, said one of the wordlines consisting of first and second lines interconnected by the source-drain path of the transistor, an intermediate signal line being connected to an input terminal of the transistor for delivering thereto an input signal from a source external to the PLA, whereby during operation of the PLA when the input signal on the intermediate signal line is a WAIT signal the flow of data along said one of the wordlines is interrupted by the transistor.
Claim 3
Dependent Claim
24 words
The PLA of claim 1 in which the transistor is an MOS transistor and the input terminal is the gate terminal of the transistor.
Claim 4
Dependent Claim
46 words
The PLA of claim 1 further comprising an input register connected for delivering data to the AND plane, an output register for receiving data from the OR plane, and at least one feedback line connected for feeding back data from the OR to the AND plane.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-12-11 | 1988-06-11 | 1988-12-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-12-11 | 1992-06-11 | 1992-12-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-12-11 | 1996-06-11 | 1996-12-11 | $7700.00 | Window Closed / Lapsed |