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US4485456A
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Data processor with R/W memory write inhibit signal
Assignee: Toshiba Corp
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Filing: 1982-04-19
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Granted: 1984-11-27
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Expires: 2002-04-19
Abstract
Abstract A main power source voltage is compared with a reference voltage, when the main power voltage drops lower than the reference voltage, an operation/halt signal is formed, a read/write memory write inhibit signal is formed in response to the operation/halt signal, and the read/write memory is inhibited in operation. This write inhibit signal is formed by setting a D-type latch at the timing of the transition of the NIF signal to active mode.
Inventors
- 👤 Shinjiro Toyoda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:02
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/24
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
73 words
A data processor comprising: an operation/halt signal input terminal; means responsive to the operation/halt signal supplied to said input terminal for forming a write inhibit signal; a read/write memory inhibited by the write inhibit signal from said signal forming means; an auxiliary power source means for energizing said signal forming means and said read/write memory; and means for comparing a main power source voltage with a reference value and forming the operation/halt signal.
Claim 2
Dependent Claim
73 words
A data processor comprising: an operation/halt signal input terminal; means responsive to the operation/halt signal supplied to said input terminal for forming a write inhibit signal; a read/write memory inhibited by the write inhibit signal from said signal forming means; an auxiliary power source means for energizing said signal forming means and said read/write memory; and means for comparing a main power source voltage with a reference value and forming the operation/halt signal.
Claim 3
Dependent Claim
17 words
The data processor according to claim 1, wherein said inhibit signal forming means comprises a D-type latch.
Claim 4
Dependent Claim
61 words
The data processor according to claim 1, wherein said operation/halt signal forming means comprises: a comparator for comparing the main power voltage with a reference voltage; an invert-NOR circuit supplied with the output from said comparator to one input terminal thereof; and means for supplying the output of said invert-NOR circuit as an operation/halt signal to the operation/halt signal input terminal.
Claim 5
Dependent Claim
25 words
The data processor according to claim 1, wherein said write inhibit signal forming means and said read/write memory are associated integrally within a 1-chip microcomputer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-11-27 | 1988-05-28 | 1988-11-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-11-27 | 1992-05-28 | 1992-11-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-11-27 | 1996-05-28 | 1996-11-27 | $7700.00 | Window Closed / Lapsed |