Lateral junction field effect transistor device

Claim 1

A lateral JFET device, which comprises: a semiconductor substrate of a first conductivity type and having a relatively light doping level; a first semiconductor layer of a second conductivity type opposite to that of the first on said substrate and having a relatively light doping level; source, gate, and drain contact regions located at the surface of said first semiconductor layer, the gate region being of the first conductivity type, more heavily doped than said substrate, and located between the source and the drain contact regions, which latter regions are of the second conductivity type and more heavily doped than said first layer; means for electrically isolating the lateral JFET device from adjacent portions of said first semiconductor layer; a surface semiconductor layer of said first conductivity type located at the surface of said first layer and between said gate and said drain contact regions, said surface layer having a doping level on the same order of magnitude as that of said substrate; and a buried semiconductor layer of said second conductivity type and having a doping level greater than that of said first semiconductor layer, said buried layer being located between said first layer and said substrate, forming a p-n isolation junction with said substrate, and extending beneath at least said drain contact region and said surface layer.