Patent US4485347A successfully refreshed from Google Patents.
US4485347A
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Digital FSK demodulator
Assignee: Mitsubishi Electric Corp
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Filing: 1981-08-17
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Granted: 1984-11-27
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Expires: 2001-08-17
Abstract
Abstract The disclosed FSK demodulator includes a digital PLL for converting an FSK modulated input signal with two different frequencies to rectangular waveforms having durations as determined by those frequencies, two reversible N bit counters for counting clock pulses to determine instantaneous duty factors in the form of N parallel bits of the waveforms for each pulse repetition period, and a read only memory for multiplying alternate outputs, except for the sign bit, from the counters by a ratio of the lower to the higher frequency of the input signal. Then, a digital first-order low-pass filter removes a high frequency component from the output of the read only memory, resulting in a demodulated binary signal. The binary signal may be produced by setting or resetting a FLIP-FLOP when the sign bit from each of the counters is respectively a binary ONE or ZERO. Alternatively, another reversible M bit counter (when M>N) may count the clock pulses to equal the output from the read only memory.
Inventors
- 👤 Shigeichi Hirasawa
- 👤 Akira Horiguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:41
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/10; H04L27/14; H04L27/156; H04L27/1566; H04L27/1563
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
320 words
A frequency shift keying demodulator comprising a rectangular waveform converter circuit for converting a frequency shift keying modulated input signal having either a high frequency or a low frequency to a signal having a rectangular waveform, a digital phase locked loop circuit for generating pulses in synchronism with the phase of said rectangular waveform from said rectangular waveform converter circuit and having pulse widths relating to said high frequency and said low frequency of said input signal, a clock pulse generator circuit for generating a train of clock pulses having a predetermined pulse repetition period, a first reversible counter for counting said clock pulses in an up direction when a pulse output from said digital phase locked loop circuit is at a high level and for counting said clock pulses in a down direction when said output from said digital phase locked loop circuit is at a low level, said clock pulses being counted between a leading edge of each pulse of said pulse output and that of the next succeeding pulse thereof, a second reversible counter for counting said clock pulses in the down direction when said output from said digital phase locked loop circuit is at a low level and for counting said clock pulses in the up direction when said output from said phase locked loop circuit is at a high level, said clock pulses being counted between a trailing edge of each pulse of said pulse output and that of the next succeeding pulse thereof, a register for deriving first and second alternating outputs from said first and second reversible counters, a read only memory for multiplying said first output from said register by a ratio of said low frequency to said high frequency of said input signal, and a digital first-order low-pass filter for removing the high frequency component from an output of said read only memory, said low-pass filter supplying a demodulated signal output.
Claim 2
Dependent Claim
320 words
A frequency shift keying demodulator comprising a rectangular waveform converter circuit for converting a frequency shift keying modulated input signal having either a high frequency or a low frequency to a signal having a rectangular waveform, a digital phase locked loop circuit for generating pulses in synchronism with the phase of said rectangular waveform from said rectangular waveform converter circuit and having pulse widths relating to said high frequency and said low frequency of said input signal, a clock pulse generator circuit for generating a train of clock pulses having a predetermined pulse repetition period, a first reversible counter for counting said clock pulses in an up direction when a pulse output from said digital phase locked loop circuit is at a high level and for counting said clock pulses in a down direction when said output from said digital phase locked loop circuit is at a low level, said clock pulses being counted between a leading edge of each pulse of said pulse output and that of the next succeeding pulse thereof, a second reversible counter for counting said clock pulses in the down direction when said output from said digital phase locked loop circuit is at a low level and for counting said clock pulses in the up direction when said output from said phase locked loop circuit is at a high level, said clock pulses being counted between a trailing edge of each pulse of said pulse output and that of the next succeeding pulse thereof, a register for deriving first and second alternating outputs from said first and second reversible counters, a read only memory for multiplying said first output from said register by a ratio of said low frequency to said high frequency of said input signal, and a digital first-order low-pass filter for removing the high frequency component from an output of said read only memory, said low-pass filter supplying a demodulated signal output.
Claim 3
Dependent Claim
118 words
A frequency shift keying demodulator as claimed in claim 2, wherein said low-pass filter comprises a rate multiplier and a subtractor, and a third reversible counter, said subtractor determining the absolute value and the sign of the difference between said output from said read only memory and an output from said third reversible counter, said rate multiplier having said clock pulses at one input and said absolute value at a second input, said rate multiplier supplying a frequency changing output in accordance with said absolute value from said subtractor, said reversible counter counting said output from said rate multiplier in either an up direction or a down direction, said direction being controlled by said sign from said subtractor.
Claim 4
Dependent Claim
110 words
A frequency shift keying demodulator as claimed in claim 1, wherein said digital first-order low-pass filter comprises a third reversible counter for counting said clock pulses, and a comparator circuit for comparing the count in said third reversible counter with said output from said read only memory so as to cause said third reversible counter to count said clock pulses in a down direction when said count in said third reversible counter is greater than said output from said read only memory and to count said clock pulses in an up direction when said count in said third reversible counter is smaller than said output from said read only memory.
Claim 5
Dependent Claim
304 words
A frequency shift keying demodulator comprising a rectangular waveform converter circuit for converting a frequency shift keying modulated input signal having either a high frequency or a low frequency to a signal having a rectangular waveform, a digital phase locked loop circuit for generating at its output pulses in synchronism with the phase of said rectangular waveform from said rectangular waveform converter circuit and having pulse widths relating to said high frequency and said low frequency of said input signal, a clock pulse generator circuit for generating a train of clock pulses having a predetermined pulse repetition period, a first reversible N bit parallel counter for counting said clock pulses in an up direction when an output from said digital phase locked loop circuit is at a high level and for counting said clock pulses in a down direction when said output from said digital phase locked loop circuit is at a low level, said clock pulses being counted between a leading edge of each pulse of said output and that of the next succeeding pulse thereof, a second reversible N bit parallel counter for counting said clock pulses in the down direction when said output from said phase locked loop circuit is at a low level and for counting said clock pulses in the up direction when said output from said phase locked loop circuit is at a high level, said clock pulses being counted between a trailing edge of each pulse of said pulse output and that of the next succeeding pulse thereof, and a FLIP-FLOP circuit which is set when the sign bit in either of said first or second reversible N bit parallel counters has a binary ONE value and is reset when said sign bit has a binary ZERO value, the output of said FLIP-FLOP supplying a demodulated signal.
Claim 6
Dependent Claim
304 words
A frequency shift keying demodulator comprising a rectangular waveform converter circuit for converting a frequency shift keying modulated input signal having either a high frequency or a low frequency to a signal having a rectangular waveform, a digital phase locked loop circuit for generating at its output pulses in synchronism with the phase of said rectangular waveform from said rectangular waveform converter circuit and having pulse widths relating to said high frequency and said low frequency of said input signal, a clock pulse generator circuit for generating a train of clock pulses having a predetermined pulse repetition period, a first reversible N bit parallel counter for counting said clock pulses in an up direction when an output from said digital phase locked loop circuit is at a high level and for counting said clock pulses in a down direction when said output from said digital phase locked loop circuit is at a low level, said clock pulses being counted between a leading edge of each pulse of said output and that of the next succeeding pulse thereof, a second reversible N bit parallel counter for counting said clock pulses in the down direction when said output from said phase locked loop circuit is at a low level and for counting said clock pulses in the up direction when said output from said phase locked loop circuit is at a high level, said clock pulses being counted between a trailing edge of each pulse of said pulse output and that of the next succeeding pulse thereof, and a FLIP-FLOP circuit which is set when the sign bit in either of said first or second reversible N bit parallel counters has a binary ONE value and is reset when said sign bit has a binary ZERO value, the output of said FLIP-FLOP supplying a demodulated signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-11-27 | 1988-05-28 | 1988-11-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-11-27 | 1992-05-28 | 1992-11-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-11-27 | 1996-05-28 | 1996-11-27 | $7700.00 | Window Closed / Lapsed |