Interface circuit for an integrated injection logic circuit

Claim 2

An interface circuit for use with an integrated injection logic circuit, comprising: first and second power source terminals; first and second resistors each having a first end connected to said first power source terminal; a current mirror circuit connected to said integrated injection logic circuit and having an input current path and an output current path, said input and output current mirror paths being respectively connected between said second power source terminal and the respective second ends of said first and second resistors, and whereby the input current value of said current mirror circuit is set by said first resistor and the input of said current mirror circuit is controlled by the output signal of said integrated injection logic circuit; and output means connected to said second end of said second resistor.

Claim 3

The interface circuit for an integrated injection logic circuit according to claim 1, in which said output means includes an emitter follower circuit comprising a transistor having its base connected to the second terminal of said second resistor and a resistor connected between the emitter and the second power source terminal.

Claim 4

The interface circuit according to claim 1, wherein said current mirror circuit comprises a first transistor, which has a collector and a base both connected to said second end of said first resistor and an emitter connected to said second power source terminal, and a second transistor, which has a collector connected to said second end of said second resistor, a base connected to said base of said first transistor and an emitter connected to said second power source terminal.

Claim 5

The interface circuit according to claim 3, wherein an emitter circuit of at least one of said first and second transistors includes a third resistor.

Claim 6

An interface circuit for an integrated injection logic circuit, comprising: first and second power source terminals; first, second and third resistors each having a first end connected to said first power source terminal; a first current mirror circuit connected to said integrated injection logic circuit and having an input current path and an output current path, said input and output current mirror paths being respectively connected between said second power source terminal and the respective second ends of said first and third resistors, whereby the input current value of said first current mirror circuit is set by said first resistor and the input of said first current mirror circuit is controlled by the output signal of said integrated injection logic circuit; a second current mirror circuit having an input current path and an output current path, said input and output current mirror paths being respectively connected between said second power source terminal and the respective second ends of said second and third resistors, and whereby the input current value of said second current mirror circuit is set by said second resistor; and output means connected to said second end of said third resistor.

Claim 7

An interface circuit for an integrated injection logic circuit, comprising: first and second power source terminals; first, second and third resistors each having a first end connected to said first power source terminal; a first current mirror circuit connected to said integrated injection logic circuit and having an input current path and an output current path, said input and output current mirror paths being respectively connected between said second power source terminal and the respective second ends of said first and third resistors, whereby the input current value of said first current mirror circuit is set by said first resistor and the input of said first current mirror circuit is controlled by the output signal of said integrated injection logic circuit; a second current mirror circuit having an input current path and an output current path, said input and output current mirror paths being respectively connected between said second power source terminal and the respective second ends of said second and third resistors, and whereby the input current value of said second current mirror circuit is set by said second resistor; and output means connected to said second end of said third resistor.

Claim 8

The interface circuit for an integrated injection logic circuit according to claim 5, in which said output means includes an emitter follower circuit comprising a transistor having its base connected to the second terminal of said third resistor and an emitter resistor.

Claim 9

The interface circuit according to claim 5, wherein said first current mirror circuit comprises a first transistor, which has a collector and a base both connected to said second end of said first resistor and an emitter connected to said second power source terminal, and a second transistor, which has a collector connected to said second end of said third resistor, a base connected to said base of said first transistor and an emitter connected to said second power source terminal, and wherein said second current mirror circuit comprises a third transistor, which has a collector and a base both connected to said second end of said second resistor and an emitter connected to said second power source terminal, and a fourth transistor, which has a collector connected to said second end of said third resistor, a base connected to said base of said third transistor and an emitter connected to said second power source terminal.

Claim 10

The interface circuit according to claim 7, wherein an emitter circuit of at least one of said first to fourth transistors includes a fourth resistor.