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US4484207A
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Static induction transistor and semiconductor integrated circuit using hetero-junction
Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
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Filing: 1983-07-26
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Granted: 1984-11-20
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Expires: 2003-07-26
Abstract
Abstract A hetero-junction static induction transistor (SIT) of normal or upside-down type to be operated by applying a forward bias across the gate and source regions, in which at least its source region and gate region among the source, drain and gate regions is formed with a material having a band gap broader than that of the channel region. Such a SIT provides a large current amplification factor, improved frequency characteristics and is suitable for high power operation and for use in semiconductor integrated circuits.
Inventors
- 👤 Jun-ichi Nishizawa
- 👤 Tadahiro Ohmi
- 👤 Nobuo Takeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:17
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/82; H10D62/824; H10D12/00; H10D64/00; H10D64/60; H10D64/602
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
97 words
A hetero-junction static induction transistor, comprising: a source semiconductor region; a drain semiconductor region, said source and drain regions having a first conductivity type and a high impurity concentration; a gate semiconductor region having a second conductivity type opposite to said first conductivity type and a high impurity concentration; a channel semiconductor region having a high resistivity; and a built-in depletion layer extending across and completely depleting said channel region, said source region and said gate region each having a band gap greater than that of said channel region and forming a hetero-junction with said channel region.
Claim 2
Dependent Claim
97 words
A hetero-junction static induction transistor, comprising: a source semiconductor region; a drain semiconductor region, said source and drain regions having a first conductivity type and a high impurity concentration; a gate semiconductor region having a second conductivity type opposite to said first conductivity type and a high impurity concentration; a channel semiconductor region having a high resistivity; and a built-in depletion layer extending across and completely depleting said channel region, said source region and said gate region each having a band gap greater than that of said channel region and forming a hetero-junction with said channel region.
Claim 3
Dependent Claim
24 words
A hetero-junction static induction transistor according to claim 1 wherein said drain region has a band gap greater than that of said channel region.
Claim 4
Dependent Claim
41 words
A hetero-junction static induction transistor according to claim 1 or 2, in which: said channel region is formed of silicon, and at least one region having a band gap greater than that of said channel region is formed with low-resistivity SIPOS.
Claim 5
Dependent Claim
51 words
A hetero-junction static induction transistor according to claim 1 or 2, in which: said channel region is formed with gallium-arsenide, and at least one region having a band gap greater than that of said channel region is formed with a semiconductor material selected from the group consisting of gallium-aluminum-arsenide and gallium-aluminum-arsenide-phosphorus.
Claim 6
Dependent Claim
20 words
A semiconductor integrated circuit containing, as a driver transistor a hetero-junction static induction transistor according to claim 1 or 2.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-11-20 | 1988-05-21 | 1988-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-11-20 | 1992-05-21 | 1992-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-11-20 | 1996-05-21 | 1996-11-20 | $7700.00 | Window Closed / Lapsed |