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US4483738A
Expired / Lapsed
US
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Method for manufacturing bipolar planar transistors
Assignee: Micronas Semiconductor Holding AG
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Filing: 1984-02-03
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Granted: 1984-11-20
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Expires: 2004-02-03
Abstract
Abstract A method of manufacturing bipolar transistors is described. The emitter areas are protected by means of an oxidation masking layer and subsequently after applying a photo-resist layer which defines the base areas two implantation processes of ions of the base zone conductivity type are performed. The one is performed with low doping dose and high acceleration voltage sufficient to render the masking layer penetrable and the other with high doping dose and low acceleration voltage as to render the masking layer impenetrable.
Inventors
- 👤 Lothar Blossfeld
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:09
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/051; H10D10/056; H10P; H10P76/00; H10P76/40; H10P76/408; H10P76/4085
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
205 words
A method for manufacturing bipolar planar transistors on a semiconductor wafer of the n-conductivity type, which is to be divided into the individual planar transistors, in which method the extrinsic base zones are produced by the implantation of p-doping ions, said method comprising the steps of: covering the emitter areas with oxidation masking layer portions, thereafter depositing a photoresist mask defining the total-base areas thereafter subjecting said wafer to two implantation steps of p-doping ions, whereby in one of said two steps p-doping ions are implanted in the exposed outer extrinsic base areas at a relatively low accelerating voltage and a relatively high dose, and in the other of said two steps p-doping ions are implanted in a small dose into the exposed extrinsic base areas and into the remaining total-base areas at such a high accelerating voltage that the oxidation masking layer portions covering the emitter areas are penetrated; removing the photoresist mask; covering the extrinsic base areas with an etch masking layer which is resistive to the etching of the oxidation masking layer portions; etching the oxidation masking layer portions; implanting dopings of the conductivity type of the emitter zones; and diffusing the base zones and the emitter zones by activating the dopings.
Claim 2
Independent Claim
205 words
A method for manufacturing bipolar planar transistors on a semiconductor wafer of the n-conductivity type, which is to be divided into the individual planar transistors, in which method the extrinsic base zones are produced by the implantation of p-doping ions, said method comprising the steps of: covering the emitter areas with oxidation masking layer portions, thereafter depositing a photoresist mask defining the total-base areas thereafter subjecting said wafer to two implantation steps of p-doping ions, whereby in one of said two steps p-doping ions are implanted in the exposed outer extrinsic base areas at a relatively low accelerating voltage and a relatively high dose, and in the other of said two steps p-doping ions are implanted in a small dose into the exposed extrinsic base areas and into the remaining total-base areas at such a high accelerating voltage that the oxidation masking layer portions covering the emitter areas are penetrated; removing the photoresist mask; covering the extrinsic base areas with an etch masking layer which is resistive to the etching of the oxidation masking layer portions; etching the oxidation masking layer portions; implanting dopings of the conductivity type of the emitter zones; and diffusing the base zones and the emitter zones by activating the dopings.
Claim 3
Dependent Claim
39 words
A method in accordance with claim 1 comprising the subsequent steps of attaching one contact pad each to the emitter zones and the base zones; dividing the semiconductor wafer into semiconductor chips each containing one pair of contact pads.
Claim 4
Dependent Claim
37 words
A method in accordance with claim 1, wherein said oxidation masking layer portions are silicon nitride and that said etch masking layer is produced by thermal oxidation of the one semiconductor surface of the extrinsic base areas.
Claim 5
Dependent Claim
28 words
A method in accordance with claim 1 wherein said semiconductor wafer comprises on its one semiconductor surface a high-resistive semiconducting layer into which the base zones are introduced.
Claim 6
Dependent Claim
28 words
A method in acccordance with claim 2, wherein said semiconductor wafer comprises on its one semiconductor surface a high-resistive semiconducting layer into which the base zones are introduced.
Claim 7
Dependent Claim
28 words
A method in accordance with claim 3, wherein said semiconductor wafer comprises on its one semiconductor surface a high-resistive semiconducting layer into which the base zones are introduced.
References Cited (Backward Citations)
US4298402A
Cited
US4347654A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-11-20 | 1988-05-21 | 1988-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-11-20 | 1992-05-21 | 1992-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-11-20 | 1996-05-21 | 1996-11-20 | $7700.00 | Window Closed / Lapsed |