Signal processor device with conditional interrupt module and multiprocessor system employing such devices

Claim 1

A signal processor device having a processor module for use in a multiprocessor system with distributed interrupt handling by at least more than one processor device, said processor module having address, data and control inputs and outputs, including an interrupt signal input for receiving an incoming interrupt request signal, comprising: at least one conditional interrupt means for comparing an identity address of said processor module upon detecting address coincidence; said conditional interrupt means being provided with: input means for receiving an external interrupt request signal with corresponding destination address; comparator means connected to said input means for comparing its own identity address with said destination address upon receiving said external interrupt request signal; output means for said comparator for transmitting a coincidence signal to said processor module when it has been established that the two said addresses are in agreement; a first gating means for gating said coincidence signal to be conditionally applied to the interrupt signal input of said signal processor module; and wherein said signal processor device has an interrupt signal output means for transmitting an outgoing interrupt request signal to outside said device characterized in that: said conditional interrupt means is further provided with a second gating means for passing an outgoing destination address from said processor module corresponding to the outgoing interrupt request; and wherein said second gating means includes a control input means serving for receiving an acknowledge signal indicating that the outgoing interrupt request has been acknowledged; and said signal processor device further including: an arbitration means having a first input for receiving a first external acknowledge signal from outside the device and a second input for passing on an outgong interrupt request signal from said processor module; and said arbitration module generating a second internal acknowledge signal if said two signals are present at a first output of said arbitration means, which second acknowledge signal is fed to control input means of said second gating means with which the outgoing interrupt request signal and the destination address are released, and at a second output of said arbitration means a third outgoing acknowledge signal appears if, upon receipt of the said first external acknowledge signal, no outgoing interrupt request signal from said processor module occurs.