Unit for prioritizing earlier and later arriving input requests

Claim 2

An asynchronous microprocessor interface unit, comprising: a transparent latch for receiving input requests; a first priority encoder coupled to the latch for determining which input request received by the latch has priority and providing a coded output; a decoder coupled to the first priority encoder to decode the coded output and providing a decoded output; a second priority encoder for also receiving the input requests and providing a coded output corresponding to the highest priority input request received; and a comparator coupled to the first and second encoders for comparing the outputs of the first and second encoders to establish a priority therebetween so that a later arriving input request which has a higher priority than an input request already processed by the first encoder can be determined.

Claim 3

The asynchronous microprocessor interface unit of claim 1 wherein the transparent latch comprises a plurality of latching means.

Claim 4

The asynchronous microprocessor interface unit of claim 1 further including means for closing the transparent latch once an input request has been received to prevent a subsequent input request from interfering.

Claim 5

An asynchronous interface unit capable of interfacing a plurality of data processors to a bus coupled to an input/output device and also capable of interfacing a single data processor to a plurality of input/output devices wherein the interfacing is done on a priority basis, the asynchronous interface unit comprising: a transparent latch for receiving input requests; a first encoder for encoding a highest priority input request received, the first encoder having an input coupled to the transparent latch and providing an encoded output; a decoder coupled to the first encoder for decoding the encoded output, a second encoder having inputs for receiving the input requests and providing outputs; and a comparator for comparing the outputs of the first and second encoders to determine whether an input request received by the second encoder is of a higher priority than the input request encoded by the first encoder; and means for closing the transparent latch so that arbitration process can be performed without interference from later arriving input request changes at the transparent latch.

Claim 6

An asynchronous interface unit capable of interfacing a plurality of data processors to a bus coupled to an input/output device and also capable of interfacing a single data processor to a plurality of input/output devices wherein the interfacing is done on a priority basis, the asynchronous interface unit comprising: a transparent latch for receiving input requests; a first encoder for encoding a highest priority input request received, the first encoder having an input coupled to the transparent latch and providing an encoded output; a decoder coupled to the first encoder for decoding the encoded output, a second encoder having inputs for receiving the input requests and providing outputs; and a comparator for comparing the outputs of the first and second encoders to determine whether an input request received by the second encoder is of a higher priority than the input request encoded by the first encoder; and means for closing the transparent latch so that arbitration process can be performed without interference from later arriving input request changes at the transparent latch.