US4481648A
Expired / Lapsed
US
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Method and system for producing a synchronous signal from _cyclic-redundancy-coded digital data blocks
Assignee: Victor Company of Japan Ltd
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Filing: 1982-07-14
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Granted: 1984-11-06
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Expires: 2002-07-14
Abstract
Abstract Each block of data having information data and redundant bits is transmitted without any synchronous signal bit word, while transmitted data is processed to find the boundary between consecutive data blocks so that a synchronous signal will be produced at the receiving end. The system for producing the synchronous signal comprises a cyclic redundancy check (CRC) circuit, a frequency divider for dividing the frequency of shift clock pulses and a reset pulse generating circuit. The reset pulse generating circuit is responsive to the output signal from the frequency divider and the shift clock pulses to produce periodically first and second reset pulses with which the CRC circuit and the frequency divider are initialized. The reset pulse generating circuit is further responsive to an error signal from the CRC circuit so that further first and second reset pulses are produced with which the CRC circuit and the frequency divider are initialized again. Initialization is repeated until the frequency divider is synchronous with the bits of the data blocks, and once synchronizm is established, the output signal from the frequency divider can be regarded as the synchronous signal indicative of the boundary between any two consecutive data blocks.
Inventors
- 👤 Yasuhiko Fujii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 07:05
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/04; H04L7/048
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
269 words
A system for producing a synchronous signal from cyclic-redundancy-coded digital data blocks, comprising: (a) a cyclic redundancy check circuit responsive to said digital data blocks and to shift clock pulses used for shifting bits of said data blocks, for producing an output error signal indicative of the presence of remainder of division of one of said digital data blocks by a predetermined generating polynominal, where said division is effected within said cyclic redundancy check circuit; (b) a frequency divider for producing an output signal by dividing the frequency of said shift clock pulses; and (c) a reset pulse generating circuit responsive to the output signal from said frequency divider and to said shift clock pulses for producing first and second reset pulses in the presence of said output signal from said frequency divider and one of said shift clock pulses, said first and second reset pulses being respectively fed to said cyclic redundancy check circuit and to said frequency divider as initializing signals, said reset pulse generating circuit being further responsive to said error signal for producing, in the presence of said error signal and one of said shift clock pulses, further first and second reset pulses with which said cyclic redundancy check circuit and said frequency divider are initialized again so that initialization is repeatedly effected until said frequency divider is synchronous with the bits of said data blocks where the output signal from said frequency divider can be regarded as said synchronous signal indicative of the boundary between two consecutive data blocks, said reset pulse generating circuit being arranged to produce said first and second reset pulses.
Claim 2
Independent Claim
269 words
A system for producing a synchronous signal from cyclic-redundancy-coded digital data blocks, comprising: (a) a cyclic redundancy check circuit responsive to said digital data blocks and to shift clock pulses used for shifting bits of said data blocks, for producing an output error signal indicative of the presence of remainder of division of one of said digital data blocks by a predetermined generating polynominal, where said division is effected within said cyclic redundancy check circuit; (b) a frequency divider for producing an output signal by dividing the frequency of said shift clock pulses; and (c) a reset pulse generating circuit responsive to the output signal from said frequency divider and to said shift clock pulses for producing first and second reset pulses in the presence of said output signal from said frequency divider and one of said shift clock pulses, said first and second reset pulses being respectively fed to said cyclic redundancy check circuit and to said frequency divider as initializing signals, said reset pulse generating circuit being further responsive to said error signal for producing, in the presence of said error signal and one of said shift clock pulses, further first and second reset pulses with which said cyclic redundancy check circuit and said frequency divider are initialized again so that initialization is repeatedly effected until said frequency divider is synchronous with the bits of said data blocks where the output signal from said frequency divider can be regarded as said synchronous signal indicative of the boundary between two consecutive data blocks, said reset pulse generating circuit being arranged to produce said first and second reset pulses.
Claim 3
Dependent Claim
317 words
A system as claimed in claim 1, wherein said reset pulse generating circuit comprises: (a) a first data latch for temporarily storing said error signal in response to the output signal from said frequency divider; (b) an error counting circuit for producing an output signal when the number of the output signals from said first data latch reaches a predetemined number within a predetermined period of time; (c) a NAND gate responsive to the output signals from said first data latch and said error counting circuit for producing an output signal; (d) a pulse generating circuit responsive to said shift clock pulses for producing a reset-timing signal which is synchronous with said shift clock pulses; (e) a second data latch for temporarily storing said output signal from said frequency divider in response to said shift clock pulses; (f) a first OR gate responsive to the output signal from said second data latch and to said reset-timing signal for producing an output signal; (g) a second OR gate responsive to the output signal from said frequency divider and to said reset-timing signal for producing an output signal; (h) a third OR gate responsive to the output signal from said NAND gate and to the output signal from said first OR gate for producing an output signal; (i) a fourth OR gate responsive to the output signal from said NAND gate and to the output signal from said second data latch; (j) a first AND gate responsive to the output signal from said third OR gate and to the output signal from said second OR gate for producing said first reset pulse as well as said further first reset pulse; and (k) a second AND gate responsive to the output signal from said fourth OR gate and to the output signal from said frequency divider for producing said second reset pulse as well as said further second reset pulse.
Claim 4
Independent Claim
217 words
A method of producing a synchronous signal from cyclic-redundancy-coded digital data blocks, comprising the steps of: (a) producing an error signal indicative of the presence of remainder of division of one of said digital data blocks by a predetermined generating polynominal by effecting cyclic redundancy check in response to shift clock pulses used for shifting bits of said data blocks, said error signal being produced by a cyclic redundancy check circuit in which said division is performed; (b) producing an output signal by dividing the frequency of said shift clock pulses by means of a frequency divider; (c) producing first and second reset pulses in the presence of the output signal from said frequency divider and to one of said shift clock pulses; (d) producing further first and second reset pulses in the presence of said error signal and one of said shift clock pulses; (e) initializing said cyclic redundancy check circuit and said frequency divider by said first and second reset pulses and by said further first and second reset pulses; and (f) repeating the step of initializing until said frequency divider is synchronized with the bits of said data blocks so that the output signal from said frequency divider can be regarded as said synchronous signal indicative of the boundary between two consecutive data blocks.
Claim 5
Independent Claim
217 words
A method of producing a synchronous signal from cyclic-redundancy-coded digital data blocks, comprising the steps of: (a) producing an error signal indicative of the presence of remainder of division of one of said digital data blocks by a predetermined generating polynominal by effecting cyclic redundancy check in response to shift clock pulses used for shifting bits of said data blocks, said error signal being produced by a cyclic redundancy check circuit in which said division is performed; (b) producing an output signal by dividing the frequency of said shift clock pulses by means of a frequency divider; (c) producing first and second reset pulses in the presence of the output signal from said frequency divider and to one of said shift clock pulses; (d) producing further first and second reset pulses in the presence of said error signal and one of said shift clock pulses; (e) initializing said cyclic redundancy check circuit and said frequency divider by said first and second reset pulses and by said further first and second reset pulses; and (f) repeating the step of initializing until said frequency divider is synchronized with the bits of said data blocks so that the output signal from said frequency divider can be regarded as said synchronous signal indicative of the boundary between two consecutive data blocks.
References Cited (Backward Citations)
US3789359A
Cited
US4375102A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-11-06 | 1988-05-07 | 1988-11-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-11-06 | 1992-05-07 | 1992-11-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-11-06 | 1996-05-07 | 1996-11-06 | $7700.00 | Window Closed / Lapsed |