Embedded memory testing method and apparatus

Claim 1

A test system for testing electronic assemblies having both combinatorial logic units and memory array units, said test system comprising: A. a memory test subsystem for applying input signals to said memory array units, for sensing outputs from said memory array units and for compiling the sensed outputs in a test routine; B. a logic test subsystem coupled to said memory test subsystem for applying inputs to said combinatorial logic units, for sensing outputs from said combinatorial logic units and for compiling the sensed outputs in a test routine; and C. a contact means coupled to said memory test subsystem and said logic test subsystem for providing electrical contact with said respective memory array units and combinatorial logic units of said electronic assemblies; D. said memory test subsystem and said logic test subsystem cooperating to place, under control of the logic test subsystem, all outputs of the logic units which connect to inputs or outputs of a memory array unit under test in a high-impedance state and to inhibit parallel operation of any other memory array unit, the outputs of which are wire-ored with the outputs of the memory array unit under test, such that said electronic assemblies are preconditioned so that each of said memory array units embedded therein can be tested in logical isolation and relative electrical isolation at said memory array unit's rated speed by said memory test subsystem by use of memory test routines.

Claim 5

A method of testing memory arrays at their rated speed in electronic assemblies having both combinatorial logic and memory arrays, said method comprising the steps of: performing a memory test comprising: A. by means of a logic test subsystem, placing in a high-impedance state the output stages of all combinatorial logic on said electronic assemblies the outputs of which connect to inputs or outputs of a target memory array to be tested; B. inhibiting the operation of any of said memory arrays that have outputs that are wire-ored with the outputs of said target memory array; C. stimulating said inputs of said target memory array by means of a memory test subsystem; D. measuring the response at said outputs of said memory array by means of said memory test subsystem; and E. returning to step A if there are other memory arrays that have not been tested; and by means of said logic test subsystem performing a combinatorial logic test including stimulating inputs of target combinatorial logic to be tested and measuring the response at the outputs of said target combinatorial logic, said memory test subsystem and said logic test subsystem cooperating such that one of said subsystems applies input signals and senses outputs while the other subsystem evaluates or analyzes sensed outputs from a prior test.

Claim 6

A method of testing memory arrays at their rated speed in electronic assemblies having both combinatorial logic and memory arrays, said method comprising the steps of: performing a memory test comprising: A. by means of a logic test subsystem, placing in a high-impedance state the output stages of all combinatorial logic on said electronic assemblies the outputs of which connect to inputs or outputs of a target memory array to be tested; B. inhibiting the operation of any of said memory arrays that have outputs that are wire-ored with the outputs of said target memory array; C. stimulating said inputs of said target memory array by means of a memory test subsystem; D. measuring the response at said outputs of said memory array by means of said memory test subsystem; and E. returning to step A if there are other memory arrays that have not been tested; and by means of said logic test subsystem performing a combinatorial logic test including stimulating inputs of target combinatorial logic to be tested and measuring the response at the outputs of said target combinatorial logic, said memory test subsystem and said logic test subsystem cooperating such that one of said subsystems applies input signals and senses outputs while the other subsystem evaluates or analyzes sensed outputs from a prior test.