US4481553A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Protection circuit
Assignee: General Electric Co
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Filing: 1982-04-05
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Granted: 1984-11-06
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Expires: 2002-04-05
Abstract
Abstract An overload protection circuit for an electrical signal source is disclosed in which an overcurrent in the signal source is sensed and the source is disabled for a predetermined time interval. If the overcurrent condition persists beyond the predetermined time interval, the turn-off cycle is repeated. The system is immune to overcurrent transients and the amplitude of the current which triggers turn-off, as well as the length of the predetermined time interval, may be selectively set.
Inventors
- 👤 Louis L. Owen
- 👤 Mark P. Horujko
- 👤 William G. Bools
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:50
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/52
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
427 words
An overcurrent protection circuit for a transistor (42) which is contained in the final stage of an amplifier (30) having an input (24), comprising: (a) a resistor (135) connected between the emitter (103) of the transistor (42) and the noninverting input of a differential amplifier (165); (b) a resistor (162) connected between the noninverting input and ground; (c) a resistor (156) connected between the inverting input of the differential amplifier (165) and a first voltage source (V1+); (d) a pair of resistors (150 and 144) connected in series between the inverting input of the differential amplifier (165) and ground, one of the resistors being variable; (e) a pulse generator connected to the output of the differential amplifier (165); (f) a resistor (177) and a capacitor (180) coupled to the pulse generator (171) for determining the duration of the pulse produced by the pulse generator; (g) a pair of resistors (195 and 201) connected in series between an output (174) of the pulse generator (171) and the base of an NPN transistor (183) and defining a node (198) therebetween; (h) a diode (204) connected between node (198) and ground and poled such that current flows from ground to node (198); (i) a resistor (189) connected between the node (198) and a negative voltage source (V2-); (j) a lead connected between the collector of the NPN transistor (183) and ground; (k) a lead connected between the emitter of the transistor (183) and the input (24) of the amplifier (30), (l) a resistor (102) connected between the emitter (103) of the transistor (42) and the first voltage source (V+), wherein, in the absence of an overcurrent condition through emitter (103), negative voltage source (V2-) turns off NPN transistor (183), thus effectively disconnecting the input (24) from ground, but in the presence of an overcurrent condition, an excursion of the voltage of the emitter (103) in a direction away from the voltage of first voltage source (V1+) causes the differential amplifier (165) to produce an amplified voltage which is substantially proportional to the difference between the voltages at its inputs, and when the amplified voltage reaches a predetermined threshold, the pulse generator produces a positive pulse which turns on transistor (183), thereby effectively connecting input (24) to ground, thereby turning off the amplifier for the duration of the pulse and then allowing the amplifier (30) to turn on again at the end of the pulse, and wherein the pulse generator (171) is activated both in response to an overcurrent through resistor (102) and in response to a short through resistor (102).
Claim 2
Dependent Claim
427 words
An overcurrent protection circuit for a transistor (42) which is contained in the final stage of an amplifier (30) having an input (24), comprising: (a) a resistor (135) connected between the emitter (103) of the transistor (42) and the noninverting input of a differential amplifier (165); (b) a resistor (162) connected between the noninverting input and ground; (c) a resistor (156) connected between the inverting input of the differential amplifier (165) and a first voltage source (V1+); (d) a pair of resistors (150 and 144) connected in series between the inverting input of the differential amplifier (165) and ground, one of the resistors being variable; (e) a pulse generator connected to the output of the differential amplifier (165); (f) a resistor (177) and a capacitor (180) coupled to the pulse generator (171) for determining the duration of the pulse produced by the pulse generator; (g) a pair of resistors (195 and 201) connected in series between an output (174) of the pulse generator (171) and the base of an NPN transistor (183) and defining a node (198) therebetween; (h) a diode (204) connected between node (198) and ground and poled such that current flows from ground to node (198); (i) a resistor (189) connected between the node (198) and a negative voltage source (V2-); (j) a lead connected between the collector of the NPN transistor (183) and ground; (k) a lead connected between the emitter of the transistor (183) and the input (24) of the amplifier (30), (l) a resistor (102) connected between the emitter (103) of the transistor (42) and the first voltage source (V+), wherein, in the absence of an overcurrent condition through emitter (103), negative voltage source (V2-) turns off NPN transistor (183), thus effectively disconnecting the input (24) from ground, but in the presence of an overcurrent condition, an excursion of the voltage of the emitter (103) in a direction away from the voltage of first voltage source (V1+) causes the differential amplifier (165) to produce an amplified voltage which is substantially proportional to the difference between the voltages at its inputs, and when the amplified voltage reaches a predetermined threshold, the pulse generator produces a positive pulse which turns on transistor (183), thereby effectively connecting input (24) to ground, thereby turning off the amplifier for the duration of the pulse and then allowing the amplifier (30) to turn on again at the end of the pulse, and wherein the pulse generator (171) is activated both in response to an overcurrent through resistor (102) and in response to a short through resistor (102).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-11-06 | 1988-05-07 | 1988-11-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-11-06 | 1992-05-07 | 1992-11-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-11-06 | 1996-05-07 | 1996-11-06 | $7700.00 | Window Closed / Lapsed |