US3927352A
Expired / Lapsed
US
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Logic system for protecting transistors
Assignee: Applied Materials Inc
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Filing: 1974-05-22
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Granted: 1975-12-16
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Expires: 1994-05-22
Abstract
Abstract System for detecting malfunctions in the operation of switching transistors in power supplies. The levels of the transistors output signals are monitored during sampling periods, and a fault is detected if the level of an output signal differs from a predetermined level. The sampling period is timed to occur at a predetermined time in the cycle of the output signal, and frequency variations can be detected as well as short circuits, open circuits and other malfunctions. Means is included for turning off the power supply in response to a fault signal and thereafter restoring power until a predetermined number of faults have occurred.
Inventors
- 👤 Douglas S Schatz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 10:03
CPC Classifications
H; H02; H02H; H02H7/00; H02H7/10; H02H7/12; H02H7/122; H02H7/1225
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
159 words
In a system for detecting a malfunction in the operation of a switching transistor turned on and off cyclically to produce a power output signal which oscillates between first and second predetermined levels at a predetermined rate: A. means for providing first and second timing signals defining first and second sampling periods during portions of alternate half cycles of the output signal; and B. logic gate means for monitoring the level of the output signal and providing a fault signal in the event that the level differs from the first or second predetermined level during the first and second sampling periods, respectively, said logic gate means comprising: 1. a first AND gate receiving inputs corresponding to the first timing signal and the output signal; 2. a second AND gate receiving inputs corresponding to the second timing signal and the inverse of the output signal; and 3. an additional gate having inputs connected to the outputs of the AND gates.
Claim 2
Dependent Claim
159 words
In a system for detecting a malfunction in the operation of a switching transistor turned on and off cyclically to produce a power output signal which oscillates between first and second predetermined levels at a predetermined rate: A. means for providing first and second timing signals defining first and second sampling periods during portions of alternate half cycles of the output signal; and B. logic gate means for monitoring the level of the output signal and providing a fault signal in the event that the level differs from the first or second predetermined level during the first and second sampling periods, respectively, said logic gate means comprising: 1. a first AND gate receiving inputs corresponding to the first timing signal and the output signal; 2. a second AND gate receiving inputs corresponding to the second timing signal and the inverse of the output signal; and 3. an additional gate having inputs connected to the outputs of the AND gates.
Claim 3
Dependent Claim
20 words
a second AND gate receiving inputs corresponding to the second timing signal and the inverse of the output signal; and
Claim 4
Dependent Claim
20 words
a second AND gate receiving inputs corresponding to the second timing signal and the inverse of the output signal; and
Claim 5
Dependent Claim
16 words
The system of claim 1 wherein the means for providing timing signals includes a one-shot multivibrator.
Claim 6
Dependent Claim
13 words
an additional gate having inputs connected to the outputs of the AND gates.
Claim 7
Dependent Claim
13 words
an additional gate having inputs connected to the outputs of the AND gates.
Claim 8
Dependent Claim
27 words
The system of claim 2 further including means for firing the one-shot multivibrator a predetermined time after the outset of a half cycle of the output signal.
Claim 9
Dependent Claim
180 words
In combination with a power supply having an oscillator for producing a signal of predetermined frequency and at least one output transistor responsive to the oscillator signal for providing a power output signal at the predetermined frequency, a protective system for the transistor comprising: A. means responsive to the oscillator signal for providing a first timing signal defining a first sampling period during a first portion of each cycle of the power output signal; B. means responsive to the first timing signal for monitoring the power output signal and providing a fault signal in the event that the level of the power output signal differs from a predetermined level during the first sampling period; C. means for providing a second timing signal defining a second sampling period during a second portion of each cycle of the power output signal; and D. means responsive to the second timing signal for monitoring the power output signal and providing a fault signal in the event that the level of the power signal differs from a second predetermined level during the second sampling period.
Claim 10
Dependent Claim
180 words
In combination with a power supply having an oscillator for producing a signal of predetermined frequency and at least one output transistor responsive to the oscillator signal for providing a power output signal at the predetermined frequency, a protective system for the transistor comprising: A. means responsive to the oscillator signal for providing a first timing signal defining a first sampling period during a first portion of each cycle of the power output signal; B. means responsive to the first timing signal for monitoring the power output signal and providing a fault signal in the event that the level of the power output signal differs from a predetermined level during the first sampling period; C. means for providing a second timing signal defining a second sampling period during a second portion of each cycle of the power output signal; and D. means responsive to the second timing signal for monitoring the power output signal and providing a fault signal in the event that the level of the power signal differs from a second predetermined level during the second sampling period.
Claim 11
Dependent Claim
17 words
The combination of claim 4 wherein the means for providing a first signal includes a one-shot multivibrator.
Claim 12
Dependent Claim
26 words
The combination of claim 5 further including means for firing the one-shot multivibrator a predetermined time after the outset of each cycle of the oscillator signal.
Claim 13
Dependent Claim
29 words
The combination of claim 4 wherein the means for monitoring the power output signal comprise logic circuit means responsive to the respective timing signals and the power output signal.
Claim 14
Dependent Claim
29 words
The combination of claim 7 wherein the logic circuit means includes logic gates having output states corresponding to the levels of the power output signal during the sampling periods.
Claim 15
Dependent Claim
176 words
In combination with a power supply having an oscillator for producing a signal of predetermined frequency and at least one output transistor responsive to the oscillator signal for providing a power output signal at the predetermined frequency, a protective system for the transistor comprising: A. means responsive to the oscillator signal for providing a timing signal defining a sampling period during a portion of each cycle of the power out signal; B. means responsive to the timing signal for monitoring the power output signal and providing a fault signal in the event that the level of the power output signal differs from a predetermined level during the sampling period; C. means for providing a second timing signal defining a second sampling period during a second portion of each cycle of the power output signal; and D. means responsive to the second timing signal for monitoring the power output signal and providing a fault signal in the event that the level of the power output signal differs from a second predetermined level during the second sampling period.
Claim 16
Dependent Claim
176 words
In combination with a power supply having an oscillator for producing a signal of predetermined frequency and at least one output transistor responsive to the oscillator signal for providing a power output signal at the predetermined frequency, a protective system for the transistor comprising: A. means responsive to the oscillator signal for providing a timing signal defining a sampling period during a portion of each cycle of the power out signal; B. means responsive to the timing signal for monitoring the power output signal and providing a fault signal in the event that the level of the power output signal differs from a predetermined level during the sampling period; C. means for providing a second timing signal defining a second sampling period during a second portion of each cycle of the power output signal; and D. means responsive to the second timing signal for monitoring the power output signal and providing a fault signal in the event that the level of the power output signal differs from a second predetermined level during the second sampling period.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-12-15 | 1979-06-16 | 1979-12-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-12-15 | 1983-06-16 | 1983-12-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-12-15 | 1987-06-16 | 1987-12-16 | $7700.00 | Window Closed / Lapsed |