Overload protection network for solid state amplifier

Claim 3

The method of claim 1, which includes the additional steps of: a. sensing the output voltage of said amplifier; and b. adding this component to that of sensing the current in the output impedance of said amplifier to produce an enhanced said electrical variation, thereby to protect said power amplifier from abnormal dissipation due to a reactive load upon the output impedance of said amplifier.

Claim 4

An abnormal output impedance protective network for a transistorized double-ended amplifier, having an input stage comprising: a. first and second auxiliary transistors 56,62 connected across first 37 and second 29 output impedances, respectively, of said double-ended amplifier, to sense excessive output current, and further connected to said double-ended amplifier to correspondingly limit the input signal drive to said double-ended amplifier; b. a first diode 68 connected to said first auxiliary transistor, to establish an amplitude threshold for conduction by subsequent auxiliary transistors; c. a third auxiliary transistor 69 connected to said first diode; d. a first time-constant circuit 73,74 connected to said third auxiliary transistor, and e. a fourth auxiliary transistor 11 connected to said input amplifying stage and to said first time constant circuit to clamp the input of the amplifier to ground for a predetermined period determined by the timer constant of said first time constant circuit, when the amplitude threshold of said first diode is exceeded because of an abnormality in said output impedance.

Claim 5

An abnormal output impedance protective network for a transistorized double-ended amplifier, having an input stage comprising: a. first and second auxiliary transistors 56,62 connected across first 37 and second 29 output impedances, respectively, of said double-ended amplifier, to sense excessive output current, and further connected to said double-ended amplifier to correspondingly limit the input signal drive to said double-ended amplifier; b. a first diode 68 connected to said first auxiliary transistor, to establish an amplitude threshold for conduction by subsequent auxiliary transistors; c. a third auxiliary transistor 69 connected to said first diode; d. a first time-constant circuit 73,74 connected to said third auxiliary transistor, and e. a fourth auxiliary transistor 11 connected to said input amplifying stage and to said first time constant circuit to clamp the input of the amplifier to ground for a predetermined period determined by the timer constant of said first time constant circuit, when the amplitude threshold of said first diode is exceeded because of an abnormality in said output impedance.

Claim 6

The network of claim 3, in which each of the connections of the first and second auxiliary transistors 56,62 across the first and second output impedances 37,29, respectively, also includes: a. a voltage divider 54,55 connected across each said output impedance 37 and connected to the corresponding auxiliary transistor 56, and the further connection to said double-ended amplifier includes; and b. a second diode 57 connected to said double-ended amplifier and to a said corresponding auxiliary transistor 56, to limit the signal drive to said transistorized double-ended amplifier.

Claim 7

The network of claim 3, in which the connection of said first diode 68 also includes: a. a limiting resistor 66, to limit the current through said firsT diode; and b. a third diode 65 connected in series with said resistor, to decouple the signal amplified by said amplifier from the protective network.

Claim 8

The network of claim 3, in which: a. said double-ended transistorized amplifier includes a power transistor connected to each of said first and second output impedances; b. said first diode 68 is a Zener diode; and c. the breakdown voltage of said Zener diode is selected to breakdown when excessive voltage of said Zener exist across each said power transistor in the presence of a degree of said excessive output current.

Claim 9

The network of claim 3, in which the connection of said fourth auxiliary transistor 11 includes: a. a bias resistor 76 connected to said first time constant circuit 73,74 and to a voltage source 10; and b. a connection from the common connection between said bias resistor and said first time constant circuit to the base of said fourth auxiliary transistor 11, to establish the clamping protection level for conduction by said fourth auxiliary transistor.

Claim 10

The network of claim 3, which additionally includes: a. a second capacitor 67 connected to said first diode 68, and to a limiting resistor 66 to form a turn-on time constant circuit to delay the start of clamping by said protective network.