Patent US4479097A successfully refreshed from Google Patents.
US4479097A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low voltage, low power RC oscillator circuit
Assignee: STMicroelectronics lnc USA
•
Filing: 1980-12-24
•
Granted: 1984-10-23
•
Expires: 2000-12-24
Abstract
Abstract A resistor-capacitor oscillator circuit (10) is provided and includes a voltage comparator circuit (12). A capacitor (20) is connected to an input terminal (14) of the voltage comparator circuit (12). A resistor divider network (30) is coupled to an input terminal (16) of the voltage comparator circuit (12) for generating a reference voltage. A delay circuit (50, 52) is coupled to an output terminal (42) of the voltage comparator circuit (12). A discharge device (54) is coupled to the delay circuit (50, 52) and to the capacitor (20) for discharging the capacitor (20). A switching device (40) is coupled to the output (42) of the voltage comparator circuit (12) and to the resistor divider network (30) for controlling the application of the reference voltage to voltage comparator circuit (12).
Inventors
- 👤 David N. Larson
- 👤 Jeffrey Ireland
- 👤 Michael B. Terry
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:59
CPC Classifications
H; H03; H03K; H03K4/00; H03K4/06; H03K4/08; H03K4/48; H03K4/50; H03K4/501
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
328 words
An oscillator circuit having first and second voltage supply sources comprising: differential amplifier means having first and second input terminals and an output terminal, said differential amplifier means generating an output signal at said output terminal and operating in active and inactive modes; capacitor means coupled to said first input terminal of said differential amplifier means and to the first voltage supply source, said capacitor means being charged during said differential amplifier means inactive mode; first switch means interconnected to said output terminal of said differential amplifier means and to the first voltage supply source; first and second resistor means, said first resistor means being connected between said first switch means and said second input terminal of said differential amplifer means, said second resistor means being connected between said second input terminal of said differential amplifier means and the second voltage supply source, such that said first and second resistor means generate a reference voltage for application to said second input terminal of said differential amplifier means during a portion of said differential amplifier means inactive mode; delay means connected to said output terminal of said differental amplifier means for delaying said output signal; second switch means coupled to said delay means and to said capacitor means for discharging said capacitor means to thereby cause said differential amplifier means to operate in said inactive mode, said discharge means activated by said output signal generated by said differential amplifier means during said differential amplifier means active mode; said first switch means activated by said output signal generated by said differential amplifier means during said differential amplifier means inactive mode for controlling generation of said reference voltage, such that said reference voltage is generated after said capacitor means has completely discharged; said delay means comprising inverter means coupled to said output terminal of said differential amplifier means, and NOR logic means having one terminal thereof coupled to said inverter means and a second input thereof coupled to a control signal.
Claim 2
Dependent Claim
328 words
An oscillator circuit having first and second voltage supply sources comprising: differential amplifier means having first and second input terminals and an output terminal, said differential amplifier means generating an output signal at said output terminal and operating in active and inactive modes; capacitor means coupled to said first input terminal of said differential amplifier means and to the first voltage supply source, said capacitor means being charged during said differential amplifier means inactive mode; first switch means interconnected to said output terminal of said differential amplifier means and to the first voltage supply source; first and second resistor means, said first resistor means being connected between said first switch means and said second input terminal of said differential amplifer means, said second resistor means being connected between said second input terminal of said differential amplifier means and the second voltage supply source, such that said first and second resistor means generate a reference voltage for application to said second input terminal of said differential amplifier means during a portion of said differential amplifier means inactive mode; delay means connected to said output terminal of said differental amplifier means for delaying said output signal; second switch means coupled to said delay means and to said capacitor means for discharging said capacitor means to thereby cause said differential amplifier means to operate in said inactive mode, said discharge means activated by said output signal generated by said differential amplifier means during said differential amplifier means active mode; said first switch means activated by said output signal generated by said differential amplifier means during said differential amplifier means inactive mode for controlling generation of said reference voltage, such that said reference voltage is generated after said capacitor means has completely discharged; said delay means comprising inverter means coupled to said output terminal of said differential amplifier means, and NOR logic means having one terminal thereof coupled to said inverter means and a second input thereof coupled to a control signal.
Claim 3
Dependent Claim
188 words
The oscillator circuit of claim 1 wherein said differential amplifier means includes: first, second, third and fourth transistor means each having first and second terminals and a control terminal; first and second current sources; said first terminal of said first transistor means being connected to said first terminal of said second transistor means and to said first terminal of said third transistor means, said second terminal of said first transistor means being connected to said second terminal of said fourth transistor means and to said first current source, said control terminal of said first transistor means comprising said second input terminal of said differential amplifier means; said second terminal of said second transistor means being connected to said first terminal of said fourth transistor means, to said control terminal of said second transistor means and to said control terminal of said third transistor means; said second terminal of said third transistor means being connected to said second current source and comprising said output terminal of said differential amplifier means; and said control terminal of said fourth transistor means comprising said first input terminal of said differential amplifier means.
Claim 4
Dependent Claim
53 words
The oscillator circuit of claim 1 wherein said second switch means comprises transistor means having first and second terminals and a control terminal, said control terminal being connected to said delay means, said first terminal being connected to said capacitor means and said second terminal being connected to the second voltage supply source.
Claim 5
Dependent Claim
59 words
The oscillator circuit of claim 1 wherein said first switch means comprises transistor means having first and second terminals and a control terminal, said control terminal being connected to said output terminal of said differential amplifier means, said first terminal being connected to the first voltage supply source and said second terminal being connected to said first resistor means.
Claim 6
Dependent Claim
24 words
The oscillator circuit of claim 1 and further including: third resistor means connected to said capacitor means and to the first voltage supply source.
References Cited (Backward Citations)
US3742384A
Cited
US3904988A
Cited
US4205279A
Cited
US4264879A
Cited
US4260959A
Cited
US4365212A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-10-23 | 1988-04-23 | 1988-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-10-23 | 1992-04-23 | 1992-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-10-23 | 1996-04-23 | 1996-10-23 | $7700.00 | Window Closed / Lapsed |