US4264879A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interval timer circuit relaxation oscillator
Assignee: NCR Voyix Corp
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Filing: 1978-12-18
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Granted: 1981-04-28
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Expires: 1998-12-18
Abstract
Abstract An interval timer circuit (similar to a relaxation oscillator) including a single comparator having first and second inputs thereto and an output therefrom. The circuit includes a first circuit leg having an R-C circuit with a control point therebetween, with said control point being connected to the second input of the comparator. A first reference voltage is established at the first input of the comparator whereby its output changes from a second state to a first state when an increasing or charging voltage at the control point exceeds the first reference voltage. A second circuit leg establishes a second reference voltage at the first input of the comparator in response to the first state at the output thereof. A third circuit leg or discharging circuit produces a decreasing voltage at the control point in response to the first state and when the decreasing voltage at the control point is less than the second reference voltage, the output of the comparator changes to its second state to repeat the process.
Inventors
- 👤 Raymond S. Duley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:36
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/023; H03K3/0231
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
347 words
An interval timer circuit comprising: a comparator having first and second inputs thereto and an output therefrom; a circuit network having a control point therein operatively coupled to said second input; first means for establishing a first reference voltage at said first input whereby the output of said comparator changes from a second state to a first state when an increasing voltage at said control point exceeds said first reference voltage; second means for establishing a second reference voltage at said first input in response to said first state of said output; said second means having only first and second ends with said first end being connected to said first input and said second end being connected to said output of said comparator; and third means for producing a decreasing voltage at said control point in response to said first state of said output whereby said output of said comparator changes to said second state when the decreasing voltage at said control point is less than said second reference voltage; said circuit network comprising first and second resistors and a capacitor being series connected to form a circuit leg which is connected between a source of potential and a reference ground of said timing circuit, said control point being located at the junction of said second resistor and said capacitor with the remaining end of said capacitor being connected to said reference ground; said first means comprising third and fourth resistors which are series connected between said source of potential and said reference ground, with the junction between said third and fourth resistors being connected to said first input of said comparator; said second means comprising a fifth resistor and a diode which are series connected between said first input and the output of said comparator, with the cathode of said diode being connected to said output; said third means comprising a second diode which is connected to a junction between said first and second resistors and the output of said comparator, with the cathode of said second diode being connected to said output of said comparator.
Claim 2
Dependent Claim
347 words
An interval timer circuit comprising: a comparator having first and second inputs thereto and an output therefrom; a circuit network having a control point therein operatively coupled to said second input; first means for establishing a first reference voltage at said first input whereby the output of said comparator changes from a second state to a first state when an increasing voltage at said control point exceeds said first reference voltage; second means for establishing a second reference voltage at said first input in response to said first state of said output; said second means having only first and second ends with said first end being connected to said first input and said second end being connected to said output of said comparator; and third means for producing a decreasing voltage at said control point in response to said first state of said output whereby said output of said comparator changes to said second state when the decreasing voltage at said control point is less than said second reference voltage; said circuit network comprising first and second resistors and a capacitor being series connected to form a circuit leg which is connected between a source of potential and a reference ground of said timing circuit, said control point being located at the junction of said second resistor and said capacitor with the remaining end of said capacitor being connected to said reference ground; said first means comprising third and fourth resistors which are series connected between said source of potential and said reference ground, with the junction between said third and fourth resistors being connected to said first input of said comparator; said second means comprising a fifth resistor and a diode which are series connected between said first input and the output of said comparator, with the cathode of said diode being connected to said output; said third means comprising a second diode which is connected to a junction between said first and second resistors and the output of said comparator, with the cathode of said second diode being connected to said output of said comparator.
Claim 3
Dependent Claim
35 words
The circuit as claimed in claim 1 in which said third, fourth, and fifth resistors have resistance values which are in the ratio of 6:12:4, respectively, and said comparator is of the open collector type.
Claim 4
Dependent Claim
35 words
The circuit as claimed in claim 1 in which said third, fourth, and fifth resistors have resistance values which are in the ratio of 6:12:4, respectively, and said comparator is of the non-open collector type.
Claim 5
Dependent Claim
199 words
An interval timer circuit comprising: a comparator having first and second inputs thereto and an output therefrom; a circuit network having a control point therein operatively coupled to said second input; first means for establishing a first reference voltage at said first input whereby the output of said comparator changes from a second state to a first state when an increasing voltage at said control point exceeds said first reference voltage; second means for establishing a second reference voltage at said first input in response to said first state of said output; said second means having only first and second ends with said first end being connected to said first input and said second end being connected to said output of said comparator; and third means for producing a decreasing voltage at said control point in response to said first state of said output whereby said output of said comparator changes to said second state when the decreasing voltage at said control point is less than said second reference voltage; said third means comprising a diode operatively coupled between said circuit network and said output of said comparator, with the cathode of said diode being connected to said output.
Claim 6
Dependent Claim
199 words
An interval timer circuit comprising: a comparator having first and second inputs thereto and an output therefrom; a circuit network having a control point therein operatively coupled to said second input; first means for establishing a first reference voltage at said first input whereby the output of said comparator changes from a second state to a first state when an increasing voltage at said control point exceeds said first reference voltage; second means for establishing a second reference voltage at said first input in response to said first state of said output; said second means having only first and second ends with said first end being connected to said first input and said second end being connected to said output of said comparator; and third means for producing a decreasing voltage at said control point in response to said first state of said output whereby said output of said comparator changes to said second state when the decreasing voltage at said control point is less than said second reference voltage; said third means comprising a diode operatively coupled between said circuit network and said output of said comparator, with the cathode of said diode being connected to said output.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-04-27 | 1984-10-27 | 1985-04-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-04-27 | 1988-10-27 | 1989-04-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-04-27 | 1992-10-27 | 1993-04-28 | $7700.00 | Window Closed / Lapsed |