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US3916342A Expired / Lapsed US ⏱️ 0.0 years remaining

Square wave generating circuit arrangement

Assignee: International Business Machines Corp
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Filing: 1974-07-10
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Granted: 1975-10-28
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Expires: 1994-07-10
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Abstract

Abstract An output wave regenerating stage following an operational amplifier stage and arranged within a dual path feedback loop delivers a symmetrical square wave of frequency and symmetry unaffected by ambient temperature and energizing supply potential variations over a broad range. Output voltages swing within the supply potential by a drop equal to the value of the Vce saturation voltage, and low grade operational amplifiers commercially available with non-symmetrical output saturation levels can be used without degrading performance.

Inventors

  • 👤 Hobart Atsushi Higuchi
  • 👤 Edward Leroy Mundrick

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 07:30
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/023; H03K3/0231

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 132 words
A square wave generating circuit arrangement comprising a pair of output terminals across which a square wave voltage is delivered, a differential amplifying circuit having one input terminal, another input terminal complementary to said one input terminal and an output terminal, a feedback loop circuit, comprising a resistive element connected between one of said voltage output terminals and said one input terminal of said amplifier circuit, a capacitive element connected between said one input terminal of said amplifier circuit and a point of fixed potential, a resistance element connected between said one voltage output terminal and said complementary input terminal of said amplifying circuit, and a square wave regenerating circuit having an input terminal directly connected to said amplifying circuit and an output terminal directly connected to said one voltage output terminal.
Claim 2
Dependent Claim 132 words
A square wave generating circuit arrangement comprising a pair of output terminals across which a square wave voltage is delivered, a differential amplifying circuit having one input terminal, another input terminal complementary to said one input terminal and an output terminal, a feedback loop circuit, comprising a resistive element connected between one of said voltage output terminals and said one input terminal of said amplifier circuit, a capacitive element connected between said one input terminal of said amplifier circuit and a point of fixed potential, a resistance element connected between said one voltage output terminal and said complementary input terminal of said amplifying circuit, and a square wave regenerating circuit having an input terminal directly connected to said amplifying circuit and an output terminal directly connected to said one voltage output terminal.
Claim 3
Dependent Claim 106 words
A square wave generating circuit arrangement as defined in claim 1 and wherein, said regenerating circuit comprising a pair of complementary transistors having collector electrodes connected in common whereby the collector-emitter electron flow paths are connected in series and each having base electrodes, said output terminal being constituted by the junction between the interconnected collector electrodes of said transistors, a direct voltage divider comprising four resistors connected in series, said input terminal being constituted by the junction between the intermediate resistors of the series, and said base electrodes of said transistors being directly and individually connected to the other junctions between the resistors of the series.
Claim 4
Dependent Claim 21 words
A square wave generating circuit arrangement as defined in claim 1 and wherein said resistance element comprises a temperature compensating component.
Claim 5
Dependent Claim 43 words
A square wave generating circuit arrangement as defined in claim 1 and incorporating a direct bias potential network connected to said complementary input terminal of said amplifying circuit and across the energizing potential supply, thereby to compensaTe for variations in the energizing supply.
Claim 6
Dependent Claim 43 words
A square wave generating circuit arrangement as defined in claim 4 and wherein, one of said output terminals, one terminal of said bias potential network, and one terminal of said source of energizing potential are all connected to said point of fixed potential.
Claim 7
Dependent Claim 102 words
A square wave generating circuit arrangement as defined in claim 1 and wherein said square wave regenerating circuit comprises a pair of complementary transistors having collector electrodes connected in common to said output terminal emitter electrodes and base electrodes, circuitry for applying energizing potential across the emitter-collector electron flow paths of said transistors in series, four resistors connected in series across said series connected emitter-collector electron flow paths, an electric connection between said input terminal and the central junction of the series connected resistors, and individual electric connections between the remaining junctions between said resistors and said base electrodes of said transistors.
Claim 8
Dependent Claim 27 words
A square wave generating circuit arrangement as defined in claim 6 and incorporating capacitors individually connected between said input terminal and said base electrodes of said transistors.
Claim 9
Dependent Claim 29 words
A square wave generating circuit arrangement as defined in claim 6 and wherein the emitter electrode of one of said transistors is connected to said point of fixed potential.
Claim 10
Dependent Claim 165 words
A square wave generating circuit arrangement comprising a pair of output terminals across which a square wave voltage is delivered, an amplifying circuit having at least one input terminal and having an output terminal, a feedback loop circuit, comprising a resistive element connected between one of said voltage output terminals and said one input terminal of said amplifying circuit, a capacitive element connected between said one input terminal of said amplifying circuit and a point of fixed potential, a pair of complementary transistors having collector electrodes connected in common to said output terminal, emitter electrodes and base electrodes, circuitry for applying energizing potential across the emitter-collector electron flow paths of said transistors in series, four resistors connected in series across said series connected emitter-collector electron flow paths, an electric connection between said output terminal of said amplifying circuit and the central junction of the series connected resistors, and individual electric connections between the remaining junctions between said resistors and said base electrodes of said transistors.
Claim 11
Dependent Claim 165 words
A square wave generating circuit arrangement comprising a pair of output terminals across which a square wave voltage is delivered, an amplifying circuit having at least one input terminal and having an output terminal, a feedback loop circuit, comprising a resistive element connected between one of said voltage output terminals and said one input terminal of said amplifying circuit, a capacitive element connected between said one input terminal of said amplifying circuit and a point of fixed potential, a pair of complementary transistors having collector electrodes connected in common to said output terminal, emitter electrodes and base electrodes, circuitry for applying energizing potential across the emitter-collector electron flow paths of said transistors in series, four resistors connected in series across said series connected emitter-collector electron flow paths, an electric connection between said output terminal of said amplifying circuit and the central junction of the series connected resistors, and individual electric connections between the remaining junctions between said resistors and said base electrodes of said transistors.

References Cited (Backward Citations)

US3482188A Cited
US3742384A Cited
US3824497A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-10-27 1979-04-28 1979-10-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-10-27 1983-04-28 1983-10-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-10-27 1987-04-28 1987-10-28 $7700.00 Window Closed / Lapsed

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