Patent US4476623A successfully refreshed from Google Patents.
US4476623A
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Method of fabricating a bipolar dynamic memory cell
Assignee: International Business Machines Corp
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Filing: 1981-07-01
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Granted: 1984-10-16
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Expires: 2001-07-01
Abstract
Abstract This describes a novel bipolar dynamic cell array with increased dielectric node capacitance and a method of making it. In the described cell a PNP transistor drives an NPN transistor so that information is stored at the base node capacitance of the PNP transistor. By using the PNP transistor as a read transistor and the NPN as a write transistor, the cell, when made in integrated form, utilizes the cell isolation capacitance to enhance the stored information without increasing the parasitic capacitances in the cell. This cell isolation capacitance can be enhanced by trenching between each cell in the array, oxidizing the trench walls and backfilling the trench with semiconductor material thereby obtaining greater contrast between 0 and 1 signals. This cell is especially useful in memory arrays.
Inventors
- 👤 Badih El-Kareh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:19
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/021; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; H10B; H10B12/00; H10B12/10; H10D; H10D84/00; H10D84/60; H10D84/65; H10W10/00; H10W10/01; H10W10/041; H10W10/40; Y; Y10; Y10S; Y10S438/00; Y10S438/901
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
247 words
A method for producing an improved complementrary transistor memory cell comprising the steps of; providing a silicon substrate of a first conductivity type, growing a silicon epitaxial layer of a second conductivity type on a surface of said substrate, diffusing an emitter and a collector region in said epitaxial layer to form a pnp transistor, diffusing an emitter region in said collector region to form a npn transistor, the base of said pnp transistor serving as the collector of said npn transistor and forming an integrated pnp-npn complementary transistor cell, reactive ion etching a plurality of channels through said epitaxial layer and said rectifying junction to expose said surface of said substrate and forming an island of said epitaxial layer, said channel being isolated from said diffused emitter and collector regions by said epitaxial layer, said island including a set of said complementary transistors, growing a silicon oxide coating on the walls of said channel to form a coating of insulating material on the bottom and walls of said channels, reactive ion etching the insulating material from the bottom of the channel over said substrate to expose said surface, and depositing a semiconductor material of the same conductivity type as said substrate on said exposed surface in said channel and in contact with coated walls thereby forming a capacitor for said complementary transistor cell with said substrate being one plate of said capacitor and said base of said pnp transistor being the other plate of said capacitor.
Claim 2
Independent Claim
247 words
A method for producing an improved complementrary transistor memory cell comprising the steps of; providing a silicon substrate of a first conductivity type, growing a silicon epitaxial layer of a second conductivity type on a surface of said substrate, diffusing an emitter and a collector region in said epitaxial layer to form a pnp transistor, diffusing an emitter region in said collector region to form a npn transistor, the base of said pnp transistor serving as the collector of said npn transistor and forming an integrated pnp-npn complementary transistor cell, reactive ion etching a plurality of channels through said epitaxial layer and said rectifying junction to expose said surface of said substrate and forming an island of said epitaxial layer, said channel being isolated from said diffused emitter and collector regions by said epitaxial layer, said island including a set of said complementary transistors, growing a silicon oxide coating on the walls of said channel to form a coating of insulating material on the bottom and walls of said channels, reactive ion etching the insulating material from the bottom of the channel over said substrate to expose said surface, and depositing a semiconductor material of the same conductivity type as said substrate on said exposed surface in said channel and in contact with coated walls thereby forming a capacitor for said complementary transistor cell with said substrate being one plate of said capacitor and said base of said pnp transistor being the other plate of said capacitor.
Claim 3
Dependent Claim
12 words
The process of claim 1 wherein said deposited semiconductor material is polycrystalline.
Claim 4
Dependent Claim
12 words
The process of claim 1 wherein said deposited semiconductor material is monocrystalline.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-10-16 | 1988-04-16 | 1988-10-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-10-16 | 1992-04-16 | 1992-10-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-10-16 | 1996-04-16 | 1996-10-16 | $7700.00 | Window Closed / Lapsed |