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Patent US4475167A successfully refreshed from Google Patents.
US4475167A
Expired / Lapsed
US
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Fast coefficient calculator for speech
Assignee: National Semiconductor Corp
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Filing: 1982-09-29
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Granted: 1984-10-02
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Expires: 2002-09-29
Abstract
Abstract A digital circuit to approximate the product of two numbers by shifting the bits in one number to higher significance positions by an amount equal to the bit position of the most significant "one" in the other number, useful in digital speech recognition and synthesis.
Inventors
- 👤 Carson Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:03
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G10; G10L; G10L25/00; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/3808; G06F2207/3852; G06F7/499; G06F7/49942; G06F7/49947
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
144 words
A digital data processing circuit for quickly approximating the product of a first binary number and a second binary number comprising: first register means to hold said first number; second register means to hold said second number; register examination means connected to said first register means and operable to determine the most significant bit position in said first register means that has a one it when said first number is held in said first register means; shifting means connected to said second register means and to said examination means, said shifting means operable to shift the contents of said second register means, toward more significant positions, by a number of positions corresponding to the most significant bit position determined by said examination means; and output means connected to said second register means operable to output the shifted second binary number as an approximate product.
Claim 2
Dependent Claim
144 words
A digital data processing circuit for quickly approximating the product of a first binary number and a second binary number comprising: first register means to hold said first number; second register means to hold said second number; register examination means connected to said first register means and operable to determine the most significant bit position in said first register means that has a one it when said first number is held in said first register means; shifting means connected to said second register means and to said examination means, said shifting means operable to shift the contents of said second register means, toward more significant positions, by a number of positions corresponding to the most significant bit position determined by said examination means; and output means connected to said second register means operable to output the shifted second binary number as an approximate product.
Claim 3
Dependent Claim
44 words
The circuit of claim 1 in which said shifting means comprises a plurality of groups of switches, each group operable to shift the digits of the second binary number a predetermined number of positions in response to an enabling signal from said examination means.
Claim 4
Dependent Claim
50 words
The circuit of claim 1 in which said register examination means comprises a decoder operable to produce a plurality of enabling signals, each of said enabling signals being produced when one of the bit positions in said first register means holds the most significant bit in said first binary number.
Claim 5
Dependent Claim
23 words
The circuit of claim 3 in which said decoder comprises a ROM coded in a manner so as to produce said enabling signals.
Claim 6
Dependent Claim
44 words
The circuit of claim 4 in which said shifting means comprises a plurality of groups of switches, each group operable to shift the digits of the second binary number a predetermined number of positions in response to an enabling signal from said examination means.
Claim 7
Dependent Claim
31 words
The circuit of claim 5 including a clearing means operable to clear said second register means unless one of the bit positions in said first register has a one in it.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-10-02 | 1988-04-02 | 1988-10-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-10-02 | 1992-04-02 | 1992-10-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-10-02 | 1996-04-02 | 1996-10-02 | $7700.00 | Window Closed / Lapsed |