Self verifying logic system

Claim 2

An electronic circuit including at least one integrated circuit chip comprising internally in combination (a) a data processing chain having an externally connectible input circuit and an externally connectible output circuit, (b) internal stimulus generator means having signal output circuits and control means coupled to and operable for activating said generator means to cause said generator means to produce a predetermined signal pattern at the said generator means signal output circuits, (c) internal stimulus generator supervisory control means having actuating means and control signals output means, said actuating means being coupled to said control signals output means and being effective when actuated to produce a sequence of control signals at said control signals output means, (d) first coupling means connecting said signal output circuits of said internal stimulus generator means internally within the chip to said data processing chain at at least one intermediate point along said chain so that said generator predetermined signal pattern is injected into said data processing chain when said generator means is activated by said generator supervisory control means, (e) second coupling means including at least a first part which connects said supervisory control means control signals output means internally within the chip to said internal stimulus generator control means effective for operating said control means to activate said generator means.

Claim 3

An electronic circuit as described in claim 1, further including fault detector means within the chip having input circuits and output circuits, said input circuits being internally coupled to and effective to monitor said data processing chain, said internal stimulus generator means and said internal stimulus generator supervisory control means, said fault detector means being effective to generator fault signals at the said output circuits upon the occurrence of a fault in the operation of said data processing chain, upon the occurrence of a fault in the operation of said internal stimulus generator means, and upon the occurrence of a fault in the operation of said internal stimulus generator supervisory control means.

Claim 4

An electronic circuit as described in claim 1 further including fault detector means within the chip having input circuits and output circuits, said input circuits being internally coupled to and effective to monitor said internal stimulus generator means, and effective to generate fault signals at the said output circuits upon the occurrence of a fault in the operation of said internal stimulus generator means.

Claim 5

An electronic circuit as described in claim 3 wherein said fault detector means monitors the accuracy of the said signal pattern at the said signal output circuits of said internal stimulus generator means.

Claim 6

An electronic circuit as described in claim 3 further including additional fault detector means within the chip having input circuits and output circuits, said input circuits being internally coupled to and effective to monitor said internal stimulus generator supervisory control means, and effective to generate fault signals at the said output circuits upon the occurrence of a fault in the operation of said internal stimulus generator supervisory control means.

Claim 7

An electronic circuit as described in claim 1 further including fault detector means within the chip having input circuits and output circuits, said input circuits being internally coupled to and effective to monitor said internal stimulus generator supervisory control means, and effective to generate fault signals at the said output circuits upon the occurrence of a fault in the operation of said internal stimulus generator supervisory control means.

Claim 8

An electronic circuit as described in claim 6 wherein said fault detector means monitors the accuracy of the said control signals at said control signals output means.

Claim 9

An electronic circuit as described in claim 1 further including fault detector means within the chip having input circuits and output circuits, said input circuits being internally coupled to and effective to monitor said data processing chain, and effective to generate fault signals at the said output circuits upon the occurrence of a fault in the operation of said data processing chain.

Claim 10

An electronic circuit as described in claim 1 further including, (a) first fault detector means within the chip having an input circuit and an output circuit, said input circuit being internally coupled to and effective to monitor said data processing chain, and effective to generate fault signals at the said output circuit upon the occurrence of a fault in the operation of said data processing chain, (b) second fault detector means within the chip having an input circuit and an output circuit, said input circuit being internally coupled to and effective to monitor said internal stimulus generator means, and effective to generate fault signals at the said output circuit upon the occurrence of a fault in the operation of said internal stimulus generator means, and (c) third fault detector means within the chip having an input circuit and an output circuit, said input circuit being internally coupled to and effective to monitor said internal stimulus generator supervisory control means, and effective to generate fault signals at the said output circuit upon the occurrence of a fault in the operation of said internal stimulus generator supervisory control means.

Claim 11

An electronic circuit as described in claim 1 wherein (a) said data processing chain includes first signal path connections for enabling said data processing chain to normally process data in a parallel load mode, and includes second signal path connections for enabling said data processing chain to process data in a serial load mode, and (b) said first coupling means connects said internal stimulus generator means signal output circuits to at least some of said second signal path connections of said data processing chain.

Claim 12

An electronic circuit as described in claim 10 wherein said second coupling means includes a second part which connects said supervisory control means control signals output means to at least some points in said data processing chain.

Claim 13

An electronic circuit as described in claim 11, further including fault detector means within the chip having input circuits and output circuits, said input circuits being internally coupled to and effective to monitor said data processing chain, said internal stimulus generator means and said internal stimulus generator supervisory control means, said fault detector means being effective to generator fault signals at the said output circuits upon the occurrence of a fault in the operation of said data processing chain, upon the occurrence of a fault in the operation of said internal stimulus generator means, and upon the occurrence of a fault in the operation of said internal stimulus generator supervisory control means.

Claim 14

An electronic circuit as described in claim 11 further including, (a) first fault detector means within the chip having input circuits and output circuits, said input circuits being internally coupled to and effective to monitor said data processing chain, and effective to generator fault signals at the said output circuits upon the occurrence of a fault in the operation of said data processing chain, (b) second fault detector means within the chip having input circuits and output circuits, said input circuits being internally coupled to and effective to monitor said internal stimulus generator means, and effective to generate fault signals at the said output circuits upon the occurrence of a fault in the operation of said internal stimulus generator means, and (c) third fault detector means within the chip having input circuits and output circuits, said input circuits being internally coupled to and effective to monitor said internal stimulus generator supervisory control means, and effective to generate fault signals at the said output circuits upon the occurrence of a fault in the operation of said internal stimulus generator supervisory control means.

Claim 15

An electronic circuit as described in claim 10 further including, (a) first fault detector means within the chip having input circuits and output circuits, said input circuits being internally coupled to and effective to monitor said data processing chain, and effective to generator fault signals at the said output circuits upon the occurrence of a fault in the operation of said data processing chain, (b) second fault detector means within the chip having input circuits and output circuits, said input circuits being internally coupled to and effective to monitor said internal stimulus generator means, and effective to generate fault signals at the said output circuits upon the occurrence of a fault in the operation of said internal stimulus generator means, and (c) third fault detector means within the chip having input circuits and output circuits, said input circuits being internally coupled to and effective to monitor said internal stimulus generator supervisory control means, and effective to generate fault signals at the said output circuits upon the occurrence of a fault in the operation of said internal stimulus generator supervisory control means.

Claim 16

An electronic circuit as described in claim 10, further including fault detector means within the chip having input circuits and output circuits, said input circuits being internally coupled to and effective to monitor said data processing chain, said internal stimulus generator means and said internal stimulus generator supervisory control means, said fault detector means being effective to generate fault signals at the said output circuits upon the occurrence of a fault in the operation of said data processing chain, upon the occurrence of a fault in the operation of said internal stimulus generator means, and upon the occurrence of a fault in the operation of said internal stimulus generator supervisory control means.

Claim 17

An electronic circuit as described in claim 1 wherein said internal stimulus generator means and first and second coupling means are each plural, the plural signal output circuits of said plural internal stimulus generator means being connected internally to plural points in said data processing chain by said plural first coupling means, and the plural control means of said plural internal stimulus generator means being connected internally to said supervisory control means control signals output means by said plural second coupling means.

Claim 18

An electronic circuit as described in claim 16 wherein (a) said data processing chain includes first signal path connections for enabling said data processing chain to normally process data in a parallel load mode, and includes second signal path connections for enabling said data processing chain to process data in a serial load mode, and (b) said first coupling means connects said internal stimulus generator means signal output circuits to at least some of said second signal path connections of said data processing chain.

Claim 19

An electronic circuit as described in claim 17 further including, (a) first fault detector means within the chip having input circuits and output circuits, said input circuits being internally coupled to and effective to monitor said data processing chain, and effective to generate fault signals at the said output circuits upon the occurrence of a fault in the operation of said data processing chain, (b) second fault detector means within the chip having input circuits and output circuits, said input circuits being internally coupled to and effective to monitor said internal stimulus generator means, and effective to generate fault signals at the said output circuits upon the occurrence of a fault in the operation of said internal stimulus generator means, and (c) third fault detector means within the chip having input circuits and output circuits, said input circuits being internally coupled to and effective to monitor said internal stimulus generator supervisory control means, and effective to generate fault signals at the said output circuits upon the occurrence of a fault in the operation of said internal stimulus generator supervisory control means.

Claim 20

An electronic circuit as described in claim 17 further including fault detector means within the chip having input circuits and output circuits, said input circuits being internally coupled to and effective to monitor said data processing chain, said internal stimulus generator means and said internal stimulus generator supervisory control means, said fault detector means being effective to generate fault signals at the said output circuits upon the occurrence of a fault in the operation of said data processing chain, upon the occurrence of a fault in the operation of said internal stimulus generator means and upon the occurrence of a fault in the operation of said internal stimulus generator supervisory control means.

Claim 21

An electronic circuit as described in claim 17 wherein said second coupling means includes a second part which connects said supervisory control means control signals output means to at least some points in said data processing chain.

Claim 22

An electronic circuit as described in claim 20 further including fault detector means within the chip having input circuits and output circuits, said input circuits being internally coupled to and effective to monitor said data processing chain, said internal stimulus generator means and said internal stimulus generator supervisory control means, said fault detector means being effective to generate fault signals at the said output circuits upon the occurrence of a fault in the operation of said data processing chain, upon the occurrence of a fault in the operation of said internal stimulus generator means and upon the occurrence of a fault in the operation of said internal stimulus generator supervisory control means.

Claim 23

An electronic circuit as described in any of claims 1, 16, 9, 13, or 20 wherein said supervisory control means actuating means is actuatable by means external to said chip.

Claim 24

An electronic circuit as described in any of claims 3, 6, 8, 9, 4, 5, 7, 13, 14, 2, 12, 15 18, 20, 19, or 21 further including an error encoding circuit within the chip having a plurality of input circuits and an output circuit, the output circuits of said fault detector means being coupled within the chip to separate ones of said plurality of input circuits of said error encoding circuit, and said error encoding circuit being effective responsive to receipt of fault signals from said fault detector means to generate at its output circuit encoded error signals designating the sources of errors in said integrated circuit chip.

Claim 25

An electronic circuit as described in claim 13 further including additional integrated circuit chips as described in claim 13 which all together comprise a plurality of integrated circuit chips interconnected in a group by an additional error encoding circuit having a plurality of input circuits and an output circuit, the output circuits of the error encoding circuit of each chip being coupled to separate ones of said plurality of input circuits of said additional error encoding circuit, and said additional error encoding circuit being effective responsive to receipt of encoded error signals from said chips error encoding circuits to generate at its output circuit encoded signals designating the sources of errors in said plurality of integrated circuit chips.

Claim 26

An electronic circuit as described in claim 24 further including a plurality of groups of integrated circuit chips as described in claim 24 interconnected by a further error encoding circuit having a plurality of input circuits and an output circuit, the output circuits of said additional error encoding circuits being coupled to separate ones of said plurality of input circuits of said further error encoding circuits, and said further error encoding circuit being effective responsive to receipt of encoded error signals from said additional error encoding circuits to generate at its output circuit encoded signals designating the sources of errors in said plurality of groups of integrated circuit chips.

Claim 27

An integrated circuit chip comprising internally in combination, (a) first and second data processing chains each having an externally connectible input circuit and an externally connectible output circuit, (b) first and second internal stimulus generator means respectively having first and second signal output circuits and first and second control means coupled to and operable for activating said first and second generator means to cause said generator means to produce predetermined signal patterns at the said generator means first and second signal output circuits, (c) first and second internal stimulus generator supervisory control means each having actuating means and first and second control signals output means, said actuating means being coupled to said first and second control signals output means and being effective when actuated to produce sequences of control signals at said first and second control signals output means, (d) first coupling means respectively connecting said first and second signal output circuits of said first and second internal stimulus generator means internally within the chip to said first and second data processing chains at intermediate points along said chains so that said first and second generator means predetermined signal patterns are injected into said first and second data processing chains when said first and second generator means are activated by said first and second supervisory control means, (e) second coupling means respectively connecting said first and second supervisory control means first and second control signals output means internally within the chip to said first and second internal stimulus generator first and second control means effective for operating said first and second control means to activate said first and second generator means.

Claim 28

An integrated circuit chip comprising internally in combination, (a) first and second data processing chains each having an externally connectible input circuit and an externally connectible output circuit, (b) first and second internal stimulus generator means respectively having first and second signal output circuits and first and second control means coupled to and operable for activating said first and second generator means to cause said generator means to produce predetermined signal patterns at the said generator means first and second signal output circuits, (c) first and second internal stimulus generator supervisory control means each having actuating means and first and second control signals output means, said actuating means being coupled to said first and second control signals output means and being effective when actuated to produce sequences of control signals at said first and second control signals output means, (d) first coupling means respectively connecting said first and second signal output circuits of said first and second internal stimulus generator means internally within the chip to said first and second data processing chains at intermediate points along said chains so that said first and second generator means predetermined signal patterns are injected into said first and second data processing chains when said first and second generator means are activated by said first and second supervisory control means, (e) second coupling means respectively connecting said first and second supervisory control means first and second control signals output means internally within the chip to said first and second internal stimulus generator first and second control means effective for operating said first and second control means to activate said first and second generator means.

Claim 29

An integrated circuit chip as described in claim 26 wherein each of said first and second internal stimulus generator means and first and second coupling means is plural, the plural signal output circuits of said plural first and second internal stimulus generator means being respectively connected internally to plural points in said first and second data processing chains by said plural first coupling means, and the plural first and second control means of said plural first and second internal stimulus generator means being respectively connected internally to said first and second supervisory control means first and second control signals output means by said plural second coupling means.

Claim 30

An integrated circuit chip as defined in claim 26 or 27 further including within the chip at least one comparator fault detector circuit having, (a) a first input circuit internally coupled to one point of said first processing chain for receiving signals therefrom, (b) a second input circuit internally coupled to a comparable logic point of said second processing chain for receiving signals therefrom, and, (c) an output circuit, said at least one comparator circuit producing at its output circuit a first signal indicating the occurrence of an error when the input signals to the said comparator represent different data and producing at its output circuit a second signal when the input signals to the said comparator represent the same data.

Claim 31

Integrated circuit chips as defined in claim 28 wherein the functional logic of said second data processing chain is a duplicate of the functional logic of said first data processing chain.

Claim 32

Integrated circuit chips as defined in claim 28 wherein the functional logic of said second data processing chain is the duplicate complementary logic to the functional logic of said first data processing chain.

Claim 33

Integrated circuit chips as defined in claim 26 or 27 wherein the functional logic of said second data processing chain is a duplicate of the functional logic of said first data processing chain.

Claim 34

Integrated circuit chips as defined in claim 26 or 27 wherein the functional logic of said second data processing chain is the duplicate complementary logic to the functional logic of said first data processing chain.