Pulse generator having variable pulse occurrence rate

Claim 2

A pulse generator circuit having oscillator input means for providing a reference frequency signal, and an output signal in which the frequency is controlled by an input word, the pulse generator circuit comprising: frequency divider means for dividing the frequency of the oscillator signal in accordance with the following formula: ##EQU5## where f o =output signal in pulses per second; f s =reference frequency signal in pulses per second; N=number of pulses available in a predetermined time interval; and P=number of pulses removed from N in the predetermined time interval by the frequency divider means; means for varying the value P between 0 and N in response to the change in value of the input word; and means for controlling the interval between the pulses in the output signal in response to the value of the input word, the frequency divider means including gating means responsive in combination to the means for controlling the interval between pulses and the reference frequency signal.

Claim 3

A pulse generator circuit having oscillator input means for providing a reference frequency signal, and an output signal in which the frequency is controlled by an input word, the pulse generator circuit comprising: frequency divider means for dividing the frequency of the oscillator signal in accordance with the following formula: ##EQU6## where f o =output signal in pulses per second; f s =reference signal in pulses per second; N=number of pulses available in a predetermined time interval; and P=number of pulses allowed in N in the predetermined time interval by the frequency divider means; means for varying the value P between 0 and N in response to the change in value of the input word; and means for controlling the interval between the pulses in the output signal in response to the value of the input word the frequency divider means including gating means responsive in combination to the means for controlling the interval between pulses and the reference frequency signal.

Claim 4

A pulse generator circuit having oscillator input means for providing a reference frequency signal, and an output signal in which the frequency is controlled by an input word, the pulse generator circuit comprising: frequency divider means for dividing the frequency of the oscillator signal in accordance with the following formula: ##EQU6## where f o =output signal in pulses per second; f s =reference signal in pulses per second; N=number of pulses available in a predetermined time interval; and P=number of pulses allowed in N in the predetermined time interval by the frequency divider means; means for varying the value P between 0 and N in response to the change in value of the input word; and means for controlling the interval between the pulses in the output signal in response to the value of the input word the frequency divider means including gating means responsive in combination to the means for controlling the interval between pulses and the reference frequency signal.

Claim 5

The pulse generator circuit of claim 1 or 2 wherein the frequency divider means comprises a state identifying means responsive to the reference frequency signal, the state identifying means having a plurality of stages for generating a number of distinct states, the number of pulses available in a predetermined time interval further comprising pulses identified by the distinct states of the state identifying means.

Claim 6

The pulse generator circuit of claim 3 wherein the state identifying means comprises a counting circuit.

Claim 7

The pulse generator circuit of claim 1 or 2 wherein the frequency divider means comprises a counting circuit responsive to the reference frequency signal, the counting circuit having a plurality of stages and generating signals indicative of periodically incrementing information values stored therein.

Claim 8

The pulse generator circuit of claim 5 wherein the means for varying the value of P between 0 and N includes means for receiving information values from the counting circuit and for receiving information values from the input word, and means for comparing the information values stored in the counting circuit with the information value of the input word and for detecting a match therebetween, the means for controlling the interval between the pulses being responsive to the detection of the match for distributing a periodic occurrence of pulses in the output signal in accordance with the information value of the input word.

Claim 9

The pulse generator circuit of claim 6 wherein the counting circuit includes multiple outputs, each of a first plurality of NAND gates being coupled to at least one of the outputs of the counting circuit for providing an output indication upon the counting circuit attaining a given count, and each of a plurality of inverter gates being coupled to at least one of the outputs of the counting circuit for providing the output indication upon the counting circuit attaining a given count, and each of a plurality of NOR gates being coupled to the output of one of the first plurality of NAND gates and to one of the multiple outputs of the counting circuit.

Claim 10

The pulse generator circuit of claim 7 wherein the means for varying the value P includes a second plurality of NAND gates, each of the second plurality of NAND gates having a first input coupled to the output of one of the plurality of NOR gates or to one of the inverter gates, and a second input connected to one of multiple values of the input word.

Claim 11

The pulse generator circuit of claim 8 wherein the means for controlling the interval between the pulses include a multiple input NAND gate, and a latch coupled to both the output of the multiple input NAND gate and the reference frequency signal provided by the oscillator input means.

Claim 12

The pulse generator circuit of claim 9 further comprising a two-input NOR gate for providing the output signal, the NOR gate having a first input connected to the latch for controlling the interval between the pulses and a second input connected to the reference frequency signal provided by the oscillator input means.

Claim 13

A pulse generator circuit having oscillator input means for providing a reference pulse source signal, and an output signal in which the frequency is controlled by an input word, the pulse generator circuit comprising: frequency reduction means for generating a pulse output signal from the reference pulse source signal in accordance with the following formula: ##EQU7## where f o =pulsing rate of the output signal; f s =pulsing rate of the source signal; N=number of pulses available from the pulse source in a predetermined time interval; and P=number of pulses selected for removal from N in the predetermined time interval by the frequency reduction means; means for individually identifying N pulses of the reference pulse source; and means for controlling the selection of P pulses for removal from N pulses in response to the value of the input word, and the frequency reduction means further comprising a first gate responsive in combination to the means for controlling the selection of P pulses and the reference pulse source signal.

Claim 14

A pulse generator circuit having oscillator input means for providing a reference pulse source signal, and an output signal in which the frequency is controlled by an input word, the pulse generator circuit comprising: frequency reduction means for generating a pulse output signal from the reference pulse source signal in accordance with the following formula: ##EQU7## where f o =pulsing rate of the output signal; f s =pulsing rate of the source signal; N=number of pulses available from the pulse source in a predetermined time interval; and P=number of pulses selected for removal from N in the predetermined time interval by the frequency reduction means; means for individually identifying N pulses of the reference pulse source; and means for controlling the selection of P pulses for removal from N pulses in response to the value of the input word, and the frequency reduction means further comprising a first gate responsive in combination to the means for controlling the selection of P pulses and the reference pulse source signal.

Claim 15

A pulse generator circuit having oscillator input means for providing a reference pulse source signal, and an output signal in which the frequency is controlled by an input word, the pulse generator circuit comprising: frequency reduction means for generating a pulse output signal from the reference pulse source signal in accordance with the following formula: ##EQU8## where f o =pulsing rate of the output signal; f s =pulsing rate of the source signal; N=number of pulses available from the pulse source in a predetermined time interval; and P=number of pulses selected to remain in N in the predetermined time interval by the frequency reduction means; means for individually identifying N pulses of the reference pulse source; and means for controlling the selection of P pulses for remaining in N pulses in response to the value of the input word, and the frequency reduction means further comprising a first gate responsive in combination to the means for controlling the selection of P pulses and the reference pulse source signal.

Claim 16

A pulse generator circuit having oscillator input means for providing a reference pulse source signal, and an output signal in which the frequency is controlled by an input word, the pulse generator circuit comprising: frequency reduction means for generating a pulse output signal from the reference pulse source signal in accordance with the following formula: ##EQU8## where f o =pulsing rate of the output signal; f s =pulsing rate of the source signal; N=number of pulses available from the pulse source in a predetermined time interval; and P=number of pulses selected to remain in N in the predetermined time interval by the frequency reduction means; means for individually identifying N pulses of the reference pulse source; and means for controlling the selection of P pulses for remaining in N pulses in response to the value of the input word, and the frequency reduction means further comprising a first gate responsive in combination to the means for controlling the selection of P pulses and the reference pulse source signal.

Claim 17

The pulse generator circuit of claim 11 or 12 wherein the means for individually identifying N pulses of the reference pulse source signal comprises a state identifying means responsive to the reference pulse source signal, the state identifying means having a plurality of stages for generating a number of distinct states, the number of pulses available in a predetermined time interval further comprising pulses identified by the distinct states of the identifying means.

Claim 18

The pulse generator circuit of claim 13 wherein the state identifying means comprises a counting circuit.

Claim 19

The pulse generator circuit of claim 11 or 12 wherein the means for individually identifying N pulses of the reference pulse source signal comprises means for generating a control signal from the reference pulse signal and a counting circuit responsive to the control signal, the counting circuit having a plurality of stages and generating signals indicative of the identity of the next occurring pulse from the reference pulse signal.

Claim 20

The pulse generator circuit of claim 14 wherein the means for controlling the selection of P pulses includes means for receiving information values from the counting circuit and for receiving information values from the input word, and means for comparing the information values stored in the counting circuit with the information value of the input word and for detecting a match therebetween.

Claim 21

The pulse generator circuit of claim 15 wherein the information values from the counting circuit comprise multiple counts and wherein the means for controlling the selection of P pulses further comprises means for decoding each of the multiple counts.

Claim 22

The pulse generator circuit of claim 17 wherein the means for decoding each of the multiple counts includes a plurality of decoder circuits, a first decoder circuit decoding a one count and a second decoder circuit decoding two counts, and the m th decoder circuit decoding 2.sup.(m-l) counts.

Claim 23

The pulse generator circuit of claim 18 wherein the pulse decoder circuits are coupled in parallel arrangement to the counting circuit, each m th decoder circuit decoding pulses that are an equal number of counts apart from the pulses decoded by the (m-l) th decoder circuit.

Claim 24

A pulse generator circuit having oscillator input means for providing a reference frequency signal, and an output signal in which the frequency is controlled by an input word, the pulse generator circuit comprising: frequency divider means for dividing the frequency of the oscillator signal in accordance with the following formula: ##EQU9## where f o =output signal in pulses per second; f s =reference frequency signal in pulses per second; N=number of pulses available in a predetermined time interval; and P=number of pulses removed from N in the predetermined time interval by the frequency divider means; means for varying the value P between 0 and N in response to the change in value of the input word; and means for controlling the interval between the pulses in the output signal in response to the value of the input word, and the frequency divider means comprising a counting circuit responsive to the reference frequency signal, the counting circuit having a plurality of stages and generating signals indicative of periodically incrementing information values stored therein, the means for varying the value of P between 0 and N including means for receiving information values from the counting circuit and for receiving information values from input word, and means for comparing the information values stored in the counting circuit with the information value of the input word and for detecting a match therebetween, the means for controlling the interval between the pulses being responsive to the detection of the match for distributing a periodic occurrence of pulses in the output signal in accordance with the information value of the input word, the counting circuit including multiple outputs, and each of a first plurality of NAND gates being coupled to at least one of the outputs of the counting circuit for providing an output indication upon the counting circuit attaining a given count, and each of a plurality of inverter gates being coupled to at least one of the outputs of the counting circuit for providing the output indication upon the counting attaining a given count, and each of a plurality of NOR gates being coupled to the output of one of the first plurality of NAND gates and to one of the multiple outputs of the counting circuit, and the means for varying the value P includes a second plurality of NAND gates, each of the second plurality of NAND gates having a first input coupled to the output of one of the plurality of NOR gates or to one of the inverter gates, and a second input connected to one of multiple values of the input word.

Claim 25

A pulse generator circuit having oscillator input means for providing a reference frequency signal, and an output signal in which the frequency is controlled by an input word, the pulse generator circuit comprising: frequency divider means for dividing the frequency of the oscillator signal in accordance with the following formula: ##EQU9## where f o =output signal in pulses per second; f s =reference frequency signal in pulses per second; N=number of pulses available in a predetermined time interval; and P=number of pulses removed from N in the predetermined time interval by the frequency divider means; means for varying the value P between 0 and N in response to the change in value of the input word; and means for controlling the interval between the pulses in the output signal in response to the value of the input word, and the frequency divider means comprising a counting circuit responsive to the reference frequency signal, the counting circuit having a plurality of stages and generating signals indicative of periodically incrementing information values stored therein, the means for varying the value of P between 0 and N including means for receiving information values from the counting circuit and for receiving information values from input word, and means for comparing the information values stored in the counting circuit with the information value of the input word and for detecting a match therebetween, the means for controlling the interval between the pulses being responsive to the detection of the match for distributing a periodic occurrence of pulses in the output signal in accordance with the information value of the input word, the counting circuit including multiple outputs, and each of a first plurality of NAND gates being coupled to at least one of the outputs of the counting circuit for providing an output indication upon the counting circuit attaining a given count, and each of a plurality of inverter gates being coupled to at least one of the outputs of the counting circuit for providing the output indication upon the counting attaining a given count, and each of a plurality of NOR gates being coupled to the output of one of the first plurality of NAND gates and to one of the multiple outputs of the counting circuit, and the means for varying the value P includes a second plurality of NAND gates, each of the second plurality of NAND gates having a first input coupled to the output of one of the plurality of NOR gates or to one of the inverter gates, and a second input connected to one of multiple values of the input word.