FET Gating circuit with fast turn-on capacitor

Claim 2

A fast turn-on FET circuit having drain and source terminals and having a switch control terminal for receiving a control potential, comprising: an enhancement mode FET having a drain, source and gate, said drain and source being connected to respective said drain and source terminals; current source means including gate resistance means connected to said gate and said switch control terminal for biasing said FET into conduction, and including control resistance means for controlling the amount of constant current supplied; and bypass capacitor means connected in parallel with said control resistance means for momentarily short-circuiting the latter to transiently couple current thereacross at turn-on such that a momentarily higher current is supplied by said current source means to said FET gate.

Claim 3

The invention according to claim 1 wherein said current source means comprises a bipolar transistor having its base-emitter voltage set by a zener diode, and wherein said control resistance means is in the emitter circuit of said bipolar transistor, and wherein the collector of said bipolar transistor is connected to said FET gate, said constant current being supplied through the emitter-collector of said bipolar transistor, said bypass capacitor means being in parallel with said control resistance means and enabling momentarily higher current through said bipolar transistor at turn-on until said bypass capacitor means is charged, whereafter said constant current is supplied through said bipolar transistor.

Claim 4

The invention according to claim 1 wherein said current source means comprises a pair of bipolar transistors connected base to base with commonly supplied emitters, the collector of one said bipolar transistor supplying current for biasing said FET gate, and the collector of the other said bipolar transistor connected to said common bases and to said control resistance means, said bypass capacitor means being in parallel with said control resistance means and enabling momentarily higher current through said other bipolar transistor to said FET gate at turn-on until said bypass capacitor means is charged, whereafter constant current is supplied through said other bipolar transistor.

Claim 5

A fast turn-on FET circuit having drain and source terminals and having a switch control terminal for receiving a control potential, comprising: an enhancement mode FET having a drain, source and gate, said drain and source being connected to respective said drain and source terminals; zener regulated current source means including gate resistance means connected to said FET gate and said switch control terminal for biasing said FET into conduction, and including control resistance means for controlling the amount of constant current supplied; and bypass capacitor means connected in parallel with said control resistance means for momentarily short-circuiting the latter to transiently couple current thereacross at turn-on such that a momentarily higher current is supplied by said zener regulated current source means to said FET gate until said bypass capacitor means is charged, whereafter said constant current is supplied.

Claim 6

A fast turn-on FET circuit having drain and source terminals and having a switch control terminal for receiving a control potential, comprising: an enhancement mode FET having a drain, source and gate, said drain and source being connected to respective said drain and source terminals; zener regulated current source means including gate resistance means connected to said FET gate and said switch control terminal for biasing said FET into conduction, and including control resistance means for controlling the amount of constant current supplied; and bypass capacitor means connected in parallel with said control resistance means for momentarily short-circuiting the latter to transiently couple current thereacross at turn-on such that a momentarily higher current is supplied by said zener regulated current source means to said FET gate until said bypass capacitor means is charged, whereafter said constant current is supplied.

Claim 7

A fast turn-on FET circuit having drain and source terminals and having a switch control terminal for receiving a control potential, comprising: an enhancement mode FET having a drain, source and gate, said drain and source being connected to respective said drain and source terminals; current mirror source means including gate resistance means connected to said FET gate and said switch control terminal for biasing said FET into conduction, and including control resistance means for controlling the amount of constant current supplied; and bypass capacitor means connected in parallel with said control resistance means for mementarily short-circuiting the latter to transiently couple current thereacross at turn-on such that a momentarily higher current is supplied by said current mirror source means to said gate until said bypass capacitor means is charged, whereafter said constant current is supplied.

Claim 8

A fast turn-on FET circuit having drain and source terminals and having a switch control terminal for receiving a control potential, comprising: an enhancement mode FET having a drain, source and gate, said drain and source being connected to respective said drain and source terminals; current mirror source means including gate resistance means connected to said FET gate and said switch control terminal for biasing said FET into conduction, and including control resistance means for controlling the amount of constant current supplied; and bypass capacitor means connected in parallel with said control resistance means for mementarily short-circuiting the latter to transiently couple current thereacross at turn-on such that a momentarily higher current is supplied by said current mirror source means to said gate until said bypass capacitor means is charged, whereafter said constant current is supplied.