Method for fabricating MESFET device using a double LOCOS process

Claim 1

A method for fabrication of MESFET devices, comprising the steps of: providing a silicon substrate; forming thick field oxide on predetermined areas of said substrate, to isolate a plurality of device areas in predetermined areas of said substrate; doping a plurality of source and drain regions within said device areas, with a heavy dose of a first-conductivity-type impurity; providing a patterned masking material over said source and drain regions, and also over a plurality of gate regions in predetermined locations within said device areas; introducing a first-type dopant into exposed portions of said substrate to form extension regions; locally oxidizing exposed portions of said substrate; removing said patterned masking material; implanting a N type dopant in the substrate in the region defined by the locally oxidized portions to form the device channel; and depositing a metal overall, and heating said metal to form silicides where said meal is in contact with silicon, whereby said silicides provide Schottky-barrier contact to said gate regions, and ohmic contact to said source and drain regions, thereby defining a plurality of MESFET devices.

Claim 2

A method for fabrication of MESFET devices, comprising the steps of: providing a silicon substrate; forming thick field oxide on predetermined areas of said substrate, to isolate a plurality of device areas in predetermined areas of said substrate; doping a plurality of source and drain regions within said device areas, with a heavy dose of a first-conductivity-type impurity; providing a patterned masking material over said source and drain regions, and also over a plurality of gate regions in predetermined locations within said device areas; introducing a first-type dopant into exposed portions of said substrate to form extension regions; locally oxidizing exposed portions of said substrate; removing said patterned masking material; implanting a N type dopant in the substrate in the region defined by the locally oxidized portions to form the device channel; and depositing a metal overall, and heating said metal to form silicides where said meal is in contact with silicon, whereby said silicides provide Schottky-barrier contact to said gate regions, and ohmic contact to said source and drain regions, thereby defining a plurality of MESFET devices.

Claim 6

A method for fabrication of MESFET devices, comprising the steps of: forming a first insulator layer on a silicon substrate; forming a second insulator layer on said first layer; patterning to define device areas in said second insulator layer; introducing a p-type dopant into the substrate through said first insulator layer, then removing remaining photoresist; thermally oxidizing the substrate to provide a patterned thick field oxide; patterning said second insulator layer; implanting n-type dopant in said substrate to create source and drain regions of the device being fabricated; removing the remainder of said second insulator layer and forming a patterned third layer of insulator over said first insulator layer; introducing n-type dopant in said substrate to determine device series resistance; thermally oxidizing to create oxide partitions between source, gate, and drain areas of said device; removing said third insulator layer; implanting an n-type dopant in the substrate under the device gate region to form the device channel; removing the remainder of said first insulator layer; depositing a layer or metal over the device area, and sintering to form metal silicide over areas where metal is in contact with substrate and did not form silicide; forming a patterned layer of metal to form device contacts and interconnections between devices.

Claim 7

A method for fabrication of MESFET devices, comprising the steps of: forming a first insulator layer on a silicon substrate; forming a second insulator layer on said first layer; patterning to define device areas in said second insulator layer; introducing a p-type dopant into the substrate through said first insulator layer, then removing remaining photoresist; thermally oxidizing the substrate to provide a patterned thick field oxide; patterning said second insulator layer; implanting n-type dopant in said substrate to create source and drain regions of the device being fabricated; removing the remainder of said second insulator layer and forming a patterned third layer of insulator over said first insulator layer; introducing n-type dopant in said substrate to determine device series resistance; thermally oxidizing to create oxide partitions between source, gate, and drain areas of said device; removing said third insulator layer; implanting an n-type dopant in the substrate under the device gate region to form the device channel; removing the remainder of said first insulator layer; depositing a layer or metal over the device area, and sintering to form metal silicide over areas where metal is in contact with substrate and did not form silicide; forming a patterned layer of metal to form device contacts and interconnections between devices.