Pad for accelerated memory test

Claim 2

A semiconductor memory having capacitive storage elements on a substrate in which each capacitive storage element has first and second electrodes, the first electrode for coupling to a bit line, comprising: a polysilicon resistor coupling a power supply bonding pad to the second electrode of the capacitive storage elements; an insulating layer between the second electrode and the substrate; and a test pad connected to the one electrode to facilitate performing an insulating layer integrity test.

Claim 3

The semiconductor memory of claim 1 wherein the integrity test provides a test voltage across the insulating layer without subjecting other nodes of the memory to abnormal voltages.

Claim 6

A semiconductor memory with capacitive storage cells formed on a substrate in which each capacitive storage element has a first electrode for receiving data, and a second electrode, comprising: a first conductive layer forming the second electrode of the capacitive storage elements separated from the substrate by a first insulating layer; a second conductive layer separated from said first conductive layer by a second insulating layer; a surface resistor insulated from the substrate having a first terminal coupled to said first conduction layer and a second terminal coupled to a power supply terminal; and a test pad connected to said first conductive layer for application of a test voltage to test the first and second insulating layers.

Claim 7

A semiconductor memory with capacitive storage cells formed on a substrate in which each capacitive storage element has a first electrode for receiving data, and a second electrode, comprising: a first conductive layer forming the second electrode of the capacitive storage elements separated from the substrate by a first insulating layer; a second conductive layer separated from said first conductive layer by a second insulating layer; a surface resistor insulated from the substrate having a first terminal coupled to said first conduction layer and a second terminal coupled to a power supply terminal; and a test pad connected to said first conductive layer for application of a test voltage to test the first and second insulating layers.

Claim 8

The semiconductor memory of claim 4 wherein the test voltage is a negative voltage.

Claim 9

The semiconductor memory of claim 4 or 5 wherein the substrate is of a first conductivity type having regions of a second conductivity type therein forming PN junctions between said regions and the substrate having a reverse bias breakdown voltage associated therewith and wherein the test voltage is of a greater magnitude than the magnitude of the reverse bias breakdown voltage.

Claim 10

The semiconductor memory of claim 4 or 5 wherein the surface resistor is a polysilicon resistor.