US4464588A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Temperature stable CMOS voltage reference
Assignee: National Semiconductor Corp
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Filing: 1982-04-01
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Granted: 1984-08-07
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Expires: 2002-04-01
Abstract
Abstract A voltage reference is developed by operating a pair of different threshold CMOS transistors as a differential linear amplifier with the reference voltage value determined as an input offset voltage. The differential amplifier consists of an input stage with controlled offset, a high gain inverter and an output stage which is directly coupled back to the inverting input. The circuit is biased up using a depletion transistor at zero bias and a current mirror configuration for supplying all stages.
Inventors
- 👤 James B. Wieser
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 10:19
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; G05F3/242; G05F3/245
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
99 words
A CMOS circuit for developing a reference potential having a value substantially independent of temperature, said circuit comprising: a first transistor of depletion construction; a second transistor of enhancement construction; means for operating said first and second transistors as the differential input stage of an operational amplifier, said input stage being operated from a source of tail current; means for biasing said first and second transistors from the output of said operational amplifier for equal conduction; and means for sensing the offset in said input stage produced by said means for biasing whereby said offset provides said reference potential.
Claim 2
Dependent Claim
99 words
A CMOS circuit for developing a reference potential having a value substantially independent of temperature, said circuit comprising: a first transistor of depletion construction; a second transistor of enhancement construction; means for operating said first and second transistors as the differential input stage of an operational amplifier, said input stage being operated from a source of tail current; means for biasing said first and second transistors from the output of said operational amplifier for equal conduction; and means for sensing the offset in said input stage produced by said means for biasing whereby said offset provides said reference potential.
Claim 3
Dependent Claim
24 words
The circuit of claim 1 wherein said first and second transistors are scaled in size to produce a pair having substantially equal transconductance values.
Claim 4
Dependent Claim
41 words
The circuit of claim 2 wherein said source of tail current is adjusted so that said first and second transistors conduct in a region where their gate to source voltage variations as a function of temperature changes are close to zero.
Claim 5
Dependent Claim
64 words
The circuit of claim 1 wherein said first and second transistors form the input stage in a differential operational amplifier that has inverting and noninverting inputs and further comprises: a high gain inverting amplifier driven from said input stage; and a low impedance output stage driven from said high gain inverting amplifier and operating to produce an output potential related to said reference potential.
Claim 6
Dependent Claim
39 words
The circuit of claim 4 wherein said input stage operates into a current mirror that drives said high gain inverting amplifier, one transistor gate comprises said amplifier noninverting input, and the other transistor gate comprises said amplifier inverting input.
Claim 7
Dependent Claim
16 words
The circuit of claim 5 wherein said output stage is directly coupled to said inverting input.
Claim 8
Dependent Claim
31 words
The circuit of claim 6 wherein the directly coupled connection between said output stage and said inverting input includes an attenuator to increase said output potential relative to said reference potential.
Claim 9
Dependent Claim
17 words
The circuit of claim 7 wherein said attenuator is digitally programmable to provide a selected output potential.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-08-07 | 1988-02-06 | 1988-08-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-08-07 | 1992-02-06 | 1992-08-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-08-07 | 1996-02-06 | 1996-08-07 | $7700.00 | Window Closed / Lapsed |