Register arithmetic device

Claim 1

An arithmetic register device which comprises: N number of n-bit arithmetic registers each having a respective lowest order flip-flop, a highest order flip-flop and intermediate order flip-flops between said lowest order flip-flop and said highest order flip-flop, a first buffer register connected to a first of said arithmetic registers for bidirectional information transfer therebetween, said first buffer register being additionally connected to a first input-output information bus; a second buffer register connected to the Nth arithmetic register for bidirectional transfer of information therebetween, said second buffer register being additionally connected to a second input-output information bus; respective first and second control buses connected to said buffer registers for controlling the transfer between said buffer registers and the arithmetic registers connected thereto; an information exchange circuit bidirectionally connected to all of said arithmetic registers for controlling information transfer therebetween such that the first register is connected to all of the other registers and every other register is also connected to a preceding and a succeeding register; an operational input bus unidirectionally connected to all of said arithmetic registers for presetting operational codes for the computation of information in said arithmetic registers; and one-digit input buses respectively connected to the control ports of the lowest order flip-flops of each of said arithmetic registers, and respective output buses connected to the control ports of the highest order flip-flops of each of said arithmetic registers to enable word-size expansion of the information words stored in said arithmetic registers.