Method of making single-level polysilicon dynamic memory array

Claim 1

A method of making an array of rows and columns of dynamic semiconductor memory cells of the one-transistor type, each cell having an access transistor and a capacitor, comprising the steps of: applying a layer of conductive material on a face of a body of semiconductor material, the layer forming a transistor gate for each said access transistor and a capacitor gate for each said capacitor overlying and separated from a capacitor area and a transistor area for each cell by thin insulator, forming heavily doped regions in said face adjacent said transistor and capacitor areas to provide a source-to-drain path for each access transistor and a connection to the capacitor area for each cell, applying an insulator coating on said face over said layer of conductive material, opening a pair of separate openings in said insulator coating for each adjacent row or cells for said transistor gate and said capacitor gate, and applying a conductive coating on said face over said insulator coating and extending into said openings, and patterning said conductive coating to define first and second parallel strips to form separate connections to the capacitor gate and the transistor gate, the strips being shared by said adjacent rows of cells, the second strips including means extending along said face to contact the transistor gates in said openings.

Claim 2

A method of making an array of rows and columns of dynamic semiconductor memory cells of the one-transistor type, each cell having an access transistor and a capacitor, comprising the steps of: applying a layer of conductive material on a face of a body of semiconductor material, the layer forming a transistor gate for each said access transistor and a capacitor gate for each said capacitor overlying and separated from a capacitor area and a transistor area for each cell by thin insulator, forming heavily doped regions in said face adjacent said transistor and capacitor areas to provide a source-to-drain path for each access transistor and a connection to the capacitor area for each cell, applying an insulator coating on said face over said layer of conductive material, opening a pair of separate openings in said insulator coating for each adjacent row or cells for said transistor gate and said capacitor gate, and applying a conductive coating on said face over said insulator coating and extending into said openings, and patterning said conductive coating to define first and second parallel strips to form separate connections to the capacitor gate and the transistor gate, the strips being shared by said adjacent rows of cells, the second strips including means extending along said face to contact the transistor gates in said openings.

Claim 9

A method of making a semiconductor device comprising the steps of: applying a layer of conductive material over a face of a semiconductor body to form first and second electrodes overlying first and second semiconductor regions, respectively, forming doped regions in said face in third and fourth regions adjacent said first and second regions, respectively, applying an insulator on said face over said layer, opening first and second holes in said insulator for connecting to said first and second electrodes, respectively, over areas generally spaced from said first and second semiconductor regions, respectively, and applying a conductive coating to said face and patterning said conductive coating to create separate first and second conductive strips extending into said first and second openings, respectively.

Claim 10

A method of making a semiconductor device comprising the steps of: applying a layer of conductive material over a face of a semiconductor body to form first and second electrodes overlying first and second semiconductor regions, respectively, forming doped regions in said face in third and fourth regions adjacent said first and second regions, respectively, applying an insulator on said face over said layer, opening first and second holes in said insulator for connecting to said first and second electrodes, respectively, over areas generally spaced from said first and second semiconductor regions, respectively, and applying a conductive coating to said face and patterning said conductive coating to create separate first and second conductive strips extending into said first and second openings, respectively.