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US4456995A
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Apparatus for high speed fault mapping of large memories
Assignee: International Business Machines Corp
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Filing: 1981-12-17
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Granted: 1984-06-26
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Expires: 2001-12-17
Abstract
Abstract PCT No. PCT/US81/01683 Sec. 371 Date Dec. 18, 1981 Sec. 102(e) Date Dec. 18, 1981 PCT Filed Dec. 17, 1981 PCT Pub. No. WO83/02164 PCT Pub. Date Jun. 23, 1983.Apparatus is disclosed for mapping and classifying the faulty bits of a large computer memory. Known data is read into the memory (1) and then the data stored in the memory is read out in a predetermined sequence (17, 18). The data read out is compared (10) with the known written data and the mismatches (errors) are counted (11, 12). Based upon the number of errors counted and the known sequence in which the stored data is read out, the type of fault is determined, e.g., a failure of an entire bit line, a failure of an entire word line, etc., and a status byte is established (7) representing the fault type. The status byte is useful in determining a reconfiguration of the memory whereby the faulty memory bits are scattered among accessed data words in such a way that available error correcting capability can correct the remaining faulty bits in each data word.
Inventors
- 👤 Philip M. Ryan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 11:19
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/88; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0706; G06F11/073; G06F11/079
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
186 words
A computer memory system comprising an array of chips (1), each said chip comprising an array of signal storage locations (FIG. 2), into which known data is introduced, means including processor means (7) for comparing (10) data read from said locations with said known data to determine the presence of faulty stored data, characterized by means (7, 6, 2, 3, 5) including said processor means for reading from said locations in a predetermined sequence, said means for comparing being connected to the last named means, first means (12, 14, 4) connected to said means for comparing and to said processor means (7) for counting a first number of faulty data read from the totallity of said locations, and second means (11, 13, 4) connected to said means for comparing and to said processor means (7) for counting a second number of sequential faulty data read from said locations, said processor means (7) receiving signals from said first (12, 14, 4) and second means (11, 13, 4) representing said first and second numbers for determining therefrom and from said predetermined sequence the type of said faulty data.
Claim 2
Dependent Claim
186 words
A computer memory system comprising an array of chips (1), each said chip comprising an array of signal storage locations (FIG. 2), into which known data is introduced, means including processor means (7) for comparing (10) data read from said locations with said known data to determine the presence of faulty stored data, characterized by means (7, 6, 2, 3, 5) including said processor means for reading from said locations in a predetermined sequence, said means for comparing being connected to the last named means, first means (12, 14, 4) connected to said means for comparing and to said processor means (7) for counting a first number of faulty data read from the totallity of said locations, and second means (11, 13, 4) connected to said means for comparing and to said processor means (7) for counting a second number of sequential faulty data read from said locations, said processor means (7) receiving signals from said first (12, 14, 4) and second means (11, 13, 4) representing said first and second numbers for determining therefrom and from said predetermined sequence the type of said faulty data.
Claim 3
Dependent Claim
22 words
The memory defined in claim 1 wherein said locations lie along word lines and said predetermined sequence is by successive word lines.
Claim 4
Dependent Claim
22 words
The memory defined in claim 1 wherein said locations lie along bit lines and said predetermined sequence is by successive bit lines.
Claim 5
Dependent Claim
31 words
The memory defined in claim 1 wherein said locations lie along word lines and bit lines and said predetermined sequence alternatively is by successive word lines and by successive bit lines.
Claim 6
Dependent Claim
17 words
The memory defined in claim 1 wherein said known data is all of the same binary type.
Claim 7
Dependent Claim
29 words
The memory defined in claim 1 wherein said second means for counting faulty data is reset each time that correct data is read out from one of said locations.
Claim 8
Dependent Claim
38 words
The memory defined in claim 1 wherein the number of faulty data is counted in two counters (11, 12), one (11) of which is reset each time that correct data is read out from one of said locations.
Claim 9
Dependent Claim
47 words
The memory defined in claim 1 wherein the number of faulty data is counted in two counters (11, 12), one (12) of which counts the total number of faulty data read outs and the other (11) of which counts the number of sequential faulty data read outs.
Claim 10
Dependent Claim
21 words
The memory defined in claim 1 wherein said processor means produces a status byte representing said type of said faulty data.
Claim 11
Dependent Claim
159 words
A computer memory system comprising an array of chips, each said chip comprising an array of signal storage locations, into which known data is introduced, means including processor means for comparing data read from said locations with said known data to determine the presence of faulty stored data, means including said processor means for reading from said locations in a predetermined sequence, said means for comparing being connected to the last named means, first means connected to said means for comparing and to said processor means for counting a first number of faulty data read from the totallity of said locations, and second means connected to sid means for comparing and to said processor means for counting a second number of sequential faulty data read from said locations, said processor means receiving signals from said first and second means representing said first and second numbers for determining therefrom and from said predetermined sequence the type of said faulty data.
Claim 12
Dependent Claim
159 words
A computer memory system comprising an array of chips, each said chip comprising an array of signal storage locations, into which known data is introduced, means including processor means for comparing data read from said locations with said known data to determine the presence of faulty stored data, means including said processor means for reading from said locations in a predetermined sequence, said means for comparing being connected to the last named means, first means connected to said means for comparing and to said processor means for counting a first number of faulty data read from the totallity of said locations, and second means connected to sid means for comparing and to said processor means for counting a second number of sequential faulty data read from said locations, said processor means receiving signals from said first and second means representing said first and second numbers for determining therefrom and from said predetermined sequence the type of said faulty data.
Claim 13
Dependent Claim
22 words
The memory defined in claim 10 wherein said locations lie along word lines and said predetermined sequence is by successive word lines.
Claim 14
Dependent Claim
22 words
The memory defined in claim 10 wherein said locations lie along bit lines and said predetermined sequence is by successive bit lines.
Claim 15
Dependent Claim
31 words
The memory defined in claim 10 wherein said locations lie along word lines and bit lines and said predetermined sequence alternatively is by successive word lines and by successive bit lines.
Claim 16
Dependent Claim
17 words
The memory defined in claim 10 wherein said known data is all of the same binary type.
Claim 17
Dependent Claim
29 words
The memory defined in claim 10 wherein said second means for counting faulty data is reset each that that correct data is read out from one of said locations.
Claim 18
Dependent Claim
35 words
The memory defined in claim 10 wherein the number of faulty data is counted in two counters, one of which is reset each time that correct data is read out from one of said locations.
Claim 19
Dependent Claim
43 words
The memory defined in claim 10 wherein the number of faulty data is counted in two counters, one of which counts the total number of faulty data read outs and the other of which counts the number of sequential faulty data read outs.
Claim 20
Dependent Claim
21 words
The memory defined in claim 10 wherein said processor means produces a status byte representing said type of said faulty data.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-06-26 | 1987-12-26 | 1988-06-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-06-26 | 1991-12-26 | 1992-06-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-06-26 | 1995-12-26 | 1996-06-26 | $7700.00 | Window Closed / Lapsed |