Isolated gate JFET structure

Claim 2

A thin channel junction field effect transistor comprising: a semiconductor body having an upper surface; a bottom gate region of said first conductivity type in said body; a thin top gate region of said first conductivity type extending from said surface into said body; a thin channel region of a second conductivity type opposite said first conductivity type contiguous to and extending between said top and bottom gate regions; a source region of said second conductivity type extending down from said surface and laterally encompassing said top gate and channel regions; a drain region of said second conductivity type extending from said surface and laterally encompassed by said top gate and channel regions; an isolation region of said second conductivity type distinct from said source and drain regions extending from said channel regions into said bottom gate region a top gate contact region of said first conductivity type extending into said isolation region and lateral encompassed at said surface by said top gate region; and said top gate and channel regions are thin relative to said source, drain, isolation and top gate contact regions..

Claim 3

The thin channel junction field effect transistor according to claim 1 wherein said source and drain regions are rectangular and include two opposed lateral walls along their length and wherein said isolation and top gate contact regions are exterior the portion of said channel regions defined by the perpendicular projection of said drain length wall on said source length wall.

Claim 4

The thin channel junction field effect transistor according to claim 2, wherein said isolation region contacts a portion of said source region exterior said portion of said source region exterior said portion of said channel region.

Claim 5

The thin channel junction field effect transistor according to claim 1, wherein said isolation region and said top gate contact region extend from said surface a greater depth than said top gate region and channel region, respectively.

Claim 6

The thin channel junction field effect transistor according to claim 8, wherein said top gate contact region extends from said surface a greater depth than said channel region.

Claim 7

The thin channel junction field effect transistor according to claim 1 wherein said isolation region has a lower impurity concentration than said source and drain regions.

Claim 8

The thin channel junction field effect transistor according to claim 1, wherein said isolation region has a lower impurity concentration than said top gate region.

Claim 9

A thin channel junction field effect transistor comprising: a semiconductor body having an upper surface; a bottom gate region of a first conductivity type in said body; a thin top gate of said first conductivity type extending from said surface into said body; a thin channel region of a second conductivity type opposite said first conductivity type contiguous to and extending down from said top gate region to said bottom gate region; a source region and a drain region of said second conductivity type spaced in and extending down from said surface and separated by said top gate and channel regions; an isolation region distinct from said source and drain regions of said second conductivity type extending from said channel region into said bottom gate region a greater depth than said channel region and contacting said channel region; a top gate contact region of said first conductivity type extending into said isolation region from said surface a greater depth that said channel region and contacting said top gate region; and said top gate and channel regions are thin relative to said source, drain, isolation and top gate contact regions.

Claim 10

A thin channel junction field effect transistor comprising: a semiconductor body having an upper surface; a bottom gate region of a first conductivity type in said body; a thin top gate of said first conductivity type extending from said surface into said body; a thin channel region of a second conductivity type opposite said first conductivity type contiguous to and extending down from said top gate region to said bottom gate region; a source region and a drain region of said second conductivity type spaced in and extending down from said surface and separated by said top gate and channel regions; an isolation region distinct from said source and drain regions of said second conductivity type extending from said channel region into said bottom gate region a greater depth than said channel region and contacting said channel region; a top gate contact region of said first conductivity type extending into said isolation region from said surface a greater depth that said channel region and contacting said top gate region; and said top gate and channel regions are thin relative to said source, drain, isolation and top gate contact regions.

Claim 11

A thin channel junction field effect transistor according to claim 8 wherein said source and drain regions are rectangular and include two opposed lateral walls along their length and wherein said isolation and top gate contact regions are exterior the portion of said top gate and channel regions defined by the perpendicular projection of said length wall of said drain region on said length wall of said source.

Claim 12

A thin channel junction field effect transistor according to claim 8 wherein said isolation region has a lower impurity concentration than said source and drain regions.

Claim 13

A thin channel junction field effect transistor according to claim 8 wherein said top gate contact region has a greater impurity concentration than said top gate region and said top gate region has a greater impurity concentration than said isolation region.

Claim 14

A thin channel junction field effect transistor according to claim 8, wherein said top gate region and said channel regions are ion implanted regions.

Claim 15

A thin channel junction field effect transistor according to claim 8, wherein said top gate region has a thickness in the range of 0.05 to 0.4 microns and said channel region has a thickness in the range of 0.1 to 0.5 microns.

Claim 16

A thin channel junction field effect transistor according to claim 8, wherein said source region laterally encompasses said top gate region to isolate it from said bottom gate region.

Claim 17

A thin channel junction field effect transistor according to claim 14, wherein said isolation region contacts said source region.

Claim 18

In a semiconductor structure including a semiconductor body having an upper surface, a first semiconductor region of a first conductivity type in said semiconductor body spaced from said upper surface, a thin second region extending from said surface into said body and of said first conductivity type, a third region of a second conductivity type opposite said first conductivity type contiguous to and extending between said first and second regions at a first depth from said upper surface, the improvement comprising: a fourth region of said second conductivity type extending down from said third region into said first region to a second depth from said surface greater than said first depth from said upper surface; a fifth region of said first conductivity type encompassed laterally at said surface by said second region and extending from said upper surface into said fourth region to form an ohmic surface contact region for said second region, wherein said fifth region is isolated from said first region by said fourth region; and sixth and seventh regions of said second conductivity type extending from said upper surface and into said first region, spaced from each other, distinct from said fourth region and in contact with said third region to provide two spaced ohmic contact regions to said third region, said second and third regions are thin relative to said fourth, sixth and seventh regions.

Claim 19

In a semiconductor structure including a semiconductor body having an upper surface, a first semiconductor region of a first conductivity type in said semiconductor body spaced from said upper surface, a thin second region extending from said surface into said body and of said first conductivity type, a third region of a second conductivity type opposite said first conductivity type contiguous to and extending between said first and second regions at a first depth from said upper surface, the improvement comprising: a fourth region of said second conductivity type extending down from said third region into said first region to a second depth from said surface greater than said first depth from said upper surface; a fifth region of said first conductivity type encompassed laterally at said surface by said second region and extending from said upper surface into said fourth region to form an ohmic surface contact region for said second region, wherein said fifth region is isolated from said first region by said fourth region; and sixth and seventh regions of said second conductivity type extending from said upper surface and into said first region, spaced from each other, distinct from said fourth region and in contact with said third region to provide two spaced ohmic contact regions to said third region, said second and third regions are thin relative to said fourth, sixth and seventh regions.

Claim 20

The semiconductor structure according to claim 16 wherein said sixth and seventh regions are rectangular and include two opposed lateral walls along their length and wherein said fourth and fifth regions are exterior the surface area defined by the perpendicular projection of said length wall of said sixth onto said length wall of said seventh region.

Claim 21

The semiconductor structure according to claim 16, wherein said sixth and seventh regions have a greater depth than said third region from said upper surface.

Claim 22

The semiconductor structure according to claim 16, wherein said fourth region has a lower impurity concentration than said second region.

Claim 23

The semiconductor structure according to claim 2, wherein said fifth region has a higher impurity concentration than said second region.