US4187514A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Junction type field effect transistor
Assignee: Toshiba Corp
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Filing: 1977-11-04
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Granted: 1980-02-05
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Expires: 1997-11-04
Abstract
Abstract A junction type field effect transistor comprising a semiconductor substrate; semiconductor regions formed in the semiconductor substrate and exposed on a major surface thereof, the semiconductor regions including a gate region and an isolation region; and a polycrystalline semiconductor layer formed on the surface of the gate region or on the surfaces of the gate region and the isolation region. The polycrystalline semiconductor layer contains an impurity of the same conductivity type as the gate and the isolation regions.
Inventors
- 👤 Yutaka Tomisawa
- 👤 Tatsuro Mitani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 12:43
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/83; H10D62/00; H10D62/80; H10D62/83; H10D64/00; H10D64/60; H10D64/62; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/30; H10D62/834; Y; Y10; Y10S; Y10S148/00; Y10S148/124
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
151 words
A junction type field effect transistor comprising: a semiconductor substrate including a semiconductor layer of one conductivity type having an exposed major surface, said substrate formed on a semiconductor body of opposite conductivity type constituting a lower gate region; semiconductor regions formed in said semiconductor layer and exposed on said major surface thereof including an exposed source region of said one conductivity type, an exposed gate region of said opposite conductivity type, an exposed drain region of said one conductivity type, an exposed isolation region of said opposite conductivity type constituting a closed path to surround said source, gate, and drain regions; said gate region having a sufficient length for said field effect transistor to attain pentode characteristics; and a polycrystalline semiconductor layer formed on the exposed surface of said gate region between said exposed drain and isolation regions, said polycrystalline semiconductor layer containing an impurity of said opposite conductivity type.
Claim 2
Dependent Claim
151 words
A junction type field effect transistor comprising: a semiconductor substrate including a semiconductor layer of one conductivity type having an exposed major surface, said substrate formed on a semiconductor body of opposite conductivity type constituting a lower gate region; semiconductor regions formed in said semiconductor layer and exposed on said major surface thereof including an exposed source region of said one conductivity type, an exposed gate region of said opposite conductivity type, an exposed drain region of said one conductivity type, an exposed isolation region of said opposite conductivity type constituting a closed path to surround said source, gate, and drain regions; said gate region having a sufficient length for said field effect transistor to attain pentode characteristics; and a polycrystalline semiconductor layer formed on the exposed surface of said gate region between said exposed drain and isolation regions, said polycrystalline semiconductor layer containing an impurity of said opposite conductivity type.
Claim 3
Dependent Claim
19 words
A field effect transistor as claimed in claim 1 wherein said polycrystalline semiconductor layer is composed of polycrystalline silicon.
Claim 4
Dependent Claim
16 words
A field effect transistor as claimed in claim 2 wherein said impurity is a P-type one.
Claim 5
Dependent Claim
31 words
A field effect transistor as claimed in claim 3 wherein said impurity is present in said polycrystalline semiconductor layer at a concentration of 10 20 to 10 21 atoms/cm 3 .
Claim 6
Dependent Claim
17 words
A field effect transistor as claimed in claim 1 wherein said gate region constitutes a closed path.
Claim 7
Dependent Claim
23 words
A field effect transistor as claimed in claim 5 wherein said polycrystalline semiconductor layer is composed of polycrystalline silicon containing a P-type impurity.
Claim 8
Dependent Claim
37 words
A field effect transistor as claimed in claim 1 wherein a plurality of gate regions are present, said gate regions being arranged in parallel with one another and spaced from one another and from said isolation region.
Claim 9
Dependent Claim
23 words
A field effect transistor as claimed in claim 7 wherein said polycrystalline semiconductor layer is composed of polycrystalline silicon containing a P-type impurity.
Claim 10
Dependent Claim
25 words
A field effect transistor as claimed in claim 1 wherein a part of said gate region formed in said semiconductor layer reaches said semiconductor body.
Claim 11
Dependent Claim
53 words
A field effect transistor as claimed in claim 1 wherein said polycrystalline semiconductor layer overlying said gate region has a metallic layer formed thereon, said metallic layer constituting an electrode a part of which is connected to said polycrystalline semiconductor layer overlying said isolation region, and said isolation region reaches said semiconductor body.
Claim 12
Dependent Claim
25 words
A field effect transistor as claimed in claim 1 wherein said polycrystalline semiconductor layer is also formed on said exposed surface of said isolation region.
Claim 13
Independent Claim
160 words
A method of manufacturing a junction type field effect transistor which comprises: forming a semiconductor substrate including a semiconductor layer of one conductivity type having an exposed major surface on a semiconductor body of opposite conductivity type; forming an insulating layer on said major surface; removing a part of said insulating layer to make a first opening forming a closed path; doping said semiconductor layer with an impurity of opposite conductivity type through said first opening to form an isolation region extending into said semiconductor body through said semiconductor layer; removing a part of the remainder of said insulating layer to make a second opening within a region surrounded by said first opening; forming in said second opening a polycrystalline semiconductor layer containing an impurity of said opposite conductivity type; and diffusing said impurity from said polycrystalline semiconductor layer into said semiconductor layer to form a gate region with sufficient length to attain pentode characteristics of said field effect transistor.
Claim 14
Independent Claim
160 words
A method of manufacturing a junction type field effect transistor which comprises: forming a semiconductor substrate including a semiconductor layer of one conductivity type having an exposed major surface on a semiconductor body of opposite conductivity type; forming an insulating layer on said major surface; removing a part of said insulating layer to make a first opening forming a closed path; doping said semiconductor layer with an impurity of opposite conductivity type through said first opening to form an isolation region extending into said semiconductor body through said semiconductor layer; removing a part of the remainder of said insulating layer to make a second opening within a region surrounded by said first opening; forming in said second opening a polycrystalline semiconductor layer containing an impurity of said opposite conductivity type; and diffusing said impurity from said polycrystalline semiconductor layer into said semiconductor layer to form a gate region with sufficient length to attain pentode characteristics of said field effect transistor.
Claim 15
Dependent Claim
29 words
A method as claimed in claim 12, comprising forming a polycrystalline semiconductor layer containing an impurity of said opposite conductivity in said first opening prior to said diffusing step.
Claim 16
Dependent Claim
17 words
A method as claimed in claim 12, wherein said polycrystalline semiconductor layers are formed of polycrystalline silicon.
References Cited (Backward Citations)
US3977017A
Cited
US3978515A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-02-04 | 1983-08-06 | 1984-02-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-02-04 | 1987-08-06 | 1988-02-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-02-04 | 1991-08-06 | 1992-02-05 | $7700.00 | Window Closed / Lapsed |