Carrier data operated squelch

Claim 1

A carrier data operated squelch circuit for use with a demodulator detector for phase shift keyed (PSK) encoded digital signals, which provides carrier clock pulses synchronized to the carrier, delayed carried clock pulses, and bit clock pulses synchronized to the edge of the bits of the digital signal, said carrier data operated squelch comprising: limiting means, for hard limiting the PSK encoded digital signal; early sampling means, coupled to the limiting means, for storing an early sample of the limited signal; transition detection means, coupled to the limiting means and the early sampling means, for generating a transition signal if the current hard limited signal is different from the stored early sample; counter means, coupled to the transition detection means, for accumulating a count by incrementing in response to detection of a transition signal and a bit clock pulse occurring concurrently with a delayed carrier clock pulse, and by decrementing in response to the absence of detection of a transition signal when a bit clock pulse occurs concurrently with a delayed carrier clock pulse; and first comparator means, coupled to the counter means, for generating a squelch control signal in response to the count exceeding a predetermined threshold.

Claim 7

A method for carrier lock detection in a communications system utilizing a demodulator detector for phase shift keyed (PSK) encoded digital signals, which provides carrier clock pulses synchronized to the carrier and bit clock pulses synchronized to the edge of the bits of the digital signal, said method comprising the steps of: hard limiting the PSK encoded digital signal; storing an early sample of the limited digital signal in response to the carrier clock pulses; generating a transition signal if the current hard limited signal is different from the stored early sample; generated carrier clock pulses delayed by a predetermined time period; incrementing a counter in response to detection of a transition signal and a bit clock pulse occurring concurrently with a delayed carrier clock pulse; decrementing the counter in response to the absence of detection of a transition signal when a bit clock pulse is detected concurrently with a delayed carrier clock pulse; and generating a squelch control signal in response to the counter contents exceeding a first predetermined threshold.

Claim 8

A method for carrier lock detection in a communications system utilizing a demodulator detector for phase shift keyed (PSK) encoded digital signals, which provides carrier clock pulses synchronized to the carrier and bit clock pulses synchronized to the edge of the bits of the digital signal, said method comprising the steps of: hard limiting the PSK encoded digital signal; storing an early sample of the limited digital signal in response to the carrier clock pulses; generating a transition signal if the current hard limited signal is different from the stored early sample; generated carrier clock pulses delayed by a predetermined time period; incrementing a counter in response to detection of a transition signal and a bit clock pulse occurring concurrently with a delayed carrier clock pulse; decrementing the counter in response to the absence of detection of a transition signal when a bit clock pulse is detected concurrently with a delayed carrier clock pulse; and generating a squelch control signal in response to the counter contents exceeding a first predetermined threshold.