Phase lock loop carrier generator for receiver of phase modulated carrier pulse signals

Claim 2

A demodulator of phase modulated carrier pulse signals in which the pulses are coded according to a plurality of N phases of the carrier, comprising a digital phase lock loop system for locking to a frequency equal to N times the carrier frequency, said phase lock loop system including at least a phase detector, a loop integrator fed from said phase detector and itself controlling a voltage controlled oscillator having an output connected to said phase detector, means for dividing by N the frequency of said oscillator and for generating a reference carrier signal, a phase comparator for comparing the phase of the carrier of said phase modulated carrier pulse signals to the phase of said reference carrier signal and for delivering a decoded signal depending on the comparison of the two latter phases, a multiphase shifter receiving the carrier of said phase modulated carrier pulse signals and locally generating a plurality of carriers having phase shifts equal to 0, 2π/N, 2×2π/N, . . . ([N/2]-1) × 2π/N with respect to said received carrier, means for generating passing through zero pulses coinciding with the passage through zero of said received and locally generated carriers, means for gating those of said passing through zero pulses which occur during the central part of each phase modulated carrier pulse and means for applying to said phase detector said gated passing through zero pulses.

Claim 3

A demodulator of phase modulated carrier pulse signals according to claim 1, in which said phase modulated carrier pulse signals have a width T and the carrier has a period 1/f, T being comprised between 1/f and 1.25/f.

Claim 4

A demodulator of phase modulated carrier pulse signals according to claim 1, in which the means for gating those of said passing through zero pulses which occur during the central part of each phase modulated carrier pulse consists in a generator of window pulses having a width comprised between the Nth and (N/2) th of the width of the phase modulated carrier pulses and in gates receiving said passing through zero pulses and said window pulses.

Claim 5

A demodulator of phase modulated carrier pulse signals in which the pulses are coded according to a plurality of N phases of the carrier, comprising: a digital phase lock loop system for locking to a frequency equal to N times the carrier frequency, said phase lock loop system including at least a phase detector, a loop integrator fed from said phase detector and itself controlling a voltage controlled oscillator, and a square pulse train generator controlled by said voltage controlled oscillator and having an output connected to said phase detector; means for dividing by N the frequency of said oscillator and generating a reference carrier signal; phase comparator means for comparing the phase of the carrier of said phase modulated carrier pulse signals to the phase of said reference carrier signal and delivering a decoded signal depending on the comparison of the two latter phases; a multiphase shifter receiving the carrier of said phase modulated carrier pulse signals and locally generating a plurality of carriers having phase shifts equal to 0, 2π/N, 2×2π/N, . . . ([N/2] - 1) × 2π/N with respect to said received carrier; means for generating passing through zero pulses coinciding with the passage through zero of said received and locally generated carriers; means for gating those of said passing through zero pulses which occur during the central part of each phase modulated carrier pulse; and means for converting in said phase detector the said gated passing through zero pulses to positive control pulses when they occur during a high of said square pulse train and to negative control pulses when they occur during a low of said square pulse train, said positive and negative control pulses acting on said voltage controlled oscillator.

Claim 6

A demodulator of phase modulated carrier pulse signals in which the pulses are coded according to a plurality of N phases of the carrier, comprising: a digital phase lock loop system for locking to a frequency equal to N times the carrier frequency, said phase lock loop system including at least a phase detector, a loop integrator fed from said phase detector and itself controlling a voltage controlled oscillator, and a square pulse train generator controlled by said voltage controlled oscillator and having an output connected to said phase detector; means for dividing by N the frequency of said oscillator and generating a reference carrier signal; phase comparator means for comparing the phase of the carrier of said phase modulated carrier pulse signals to the phase of said reference carrier signal and delivering a decoded signal depending on the comparison of the two latter phases; a multiphase shifter receiving the carrier of said phase modulated carrier pulse signals and locally generating a plurality of carriers having phase shifts equal to 0, 2π/N, 2×2π/N, . . . ([N/2] - 1) × 2π/N with respect to said received carrier; means for generating passing through zero pulses coinciding with the passage through zero of said received and locally generated carriers; means for gating those of said passing through zero pulses which occur during the central part of each phase modulated carrier pulse; and means for converting in said phase detector the said gated passing through zero pulses to positive control pulses when they occur during a high of said square pulse train and to negative control pulses when they occur during a low of said square pulse train, said positive and negative control pulses acting on said voltage controlled oscillator.

Claim 7

A demodulator of phase modulated carrier pulse signals in which the pulses are coded according to a plurality of N phases of the carrier, comprising: a digital phase lock loop system for locking to a frequency equal to N times the carrier frequency, said phase lock loop system including at least a phase detector, a loop integrator, fed from said phase detector and itself controlling a voltage controlled oscillator, and a square pulse train generator controlled by said voltage controlled oscillator and having an output connected to said phase detector; means for dividing by N the frequency of said oscillator and generating a reference carrier signal; phase comparator for comparing the phase of the carrier of said phase modulated carrier pulse signals to the phase of said reference carrier signal and delivering a decoded signal depending on the comparison of the two latter phases; a multiphase shifter receiving the carrier of said pulse modulated carrier pulse signals and locally generating a plurality of carriers having phase shifts equal to 0, 2π/N, 2×2π/N, . . . ([N/2] - 1) × 2π/N with respect to said received carrier; means for generating passing through zero pulses coinciding with the passage through zero of said received and locally generated carriers; means for gating those of said passing through zero pulses which occur during the central part of each phase modulated carrier pulse; means for converting in said phase detector the said gated passing through zero pulses to positive control pulses when they occur during a high of said square pulse train and to negative control pulses when they occur during a low of said square pulse train, said positive and negative control pulses acting on said voltage controlled oscillator; means for phase shifting by π/2 said square pulse train; and a control circuit for controlling the phase lock loop circuit integrator by making it operative or not, said control circuit receiving said gated passing through zero pulses and said phase shifted square pulse train and generating a control signal when said gated passing through zero pulses occur during a low of said phase shifted square pulse train.

Claim 8

A demodulator of phase modulated carrier pulse signals in which the pulses are coded according to a plurality of N phases of the carrier, comprising: a digital phase lock loop system for locking to a frequency equal to N times the carrier frequency, said phase lock loop system including at least a phase detector, a loop integrator, fed from said phase detector and itself controlling a voltage controlled oscillator, and a square pulse train generator controlled by said voltage controlled oscillator and having an output connected to said phase detector; means for dividing by N the frequency of said oscillator and generating a reference carrier signal; phase comparator for comparing the phase of the carrier of said phase modulated carrier pulse signals to the phase of said reference carrier signal and delivering a decoded signal depending on the comparison of the two latter phases; a multiphase shifter receiving the carrier of said pulse modulated carrier pulse signals and locally generating a plurality of carriers having phase shifts equal to 0, 2π/N, 2×2π/N, . . . ([N/2] - 1) × 2π/N with respect to said received carrier; means for generating passing through zero pulses coinciding with the passage through zero of said received and locally generated carriers; means for gating those of said passing through zero pulses which occur during the central part of each phase modulated carrier pulse; means for converting in said phase detector the said gated passing through zero pulses to positive control pulses when they occur during a high of said square pulse train and to negative control pulses when they occur during a low of said square pulse train, said positive and negative control pulses acting on said voltage controlled oscillator; means for phase shifting by π/2 said square pulse train; and a control circuit for controlling the phase lock loop circuit integrator by making it operative or not, said control circuit receiving said gated passing through zero pulses and said phase shifted square pulse train and generating a control signal when said gated passing through zero pulses occur during a low of said phase shifted square pulse train.