US4451922A
Expired / Lapsed
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Transmission logic parity circuit
Assignee: International Business Machines Corp
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Filing: 1981-12-21
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Granted: 1984-05-29
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Expires: 2001-12-21
Abstract
Abstract An FET transmission logic parity circuit is disclosed which determines the odd or even status of register bits using zero DC current transmission logic. The circuit has a first two FET devices which propagate the state of the preceding odd or even nodes and the corresponding register bit is logically a zero. A second pair of FET devices switch the state of the odd or even nodes when the corresponding register bit is logically a one. In this manner, the output nodes are statically conditioned to either a first potential or a second potential, depending upon the register bit states and no DC current flows between the first and second potential.
Inventors
- 👤 Ziba T. Dearden
- 👤 Yogi K. Puri
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 02:08
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
605 words
A parity circuit for determining whether an odd or even number of binary bits having an even number of binary bits having a value of one, are present, at an n-bit plurality of binary operand bit inputs, comprising: n-stages of sequentially connected steering cells, each said cell including a true-value binary bit operand input and a complementary-value binary bit operand input for one said plurality of operand bit inputs, a first and a second indicating potential input terminals and a first and a second indicating potential output terminals; said first indicating potential input terminal of an i-th cell connected to said first indicating potential output terminal of the next preceding i+1th cell and said second indicating potential input terminal of said i-th cell connected to said second indicating potential output terminal of said next preceding i+1th cell; a first FET device in each said cell having its drain connected to said first indicating potential input terminal thereof, its source connected to said first indicating potential output terminal thereof, and its gate connected to said complementary-value binary bit operand input thereof; a second FET device in each said cell having its drain connected to said second indicating potential input terminal thereof, its source connected to said first indicating potential output terminal thereof, and its gate connected to said true-value binary bit operand input thereof; a third FET device in each said cell having its drain connected to said first indicating potential input terminal thereof, its source connected to said second indicating potential output terminal thereof, and its gate connected to said true-value binary bit operand input thereof; a fourth FET device in each said cell having its drain connected to said second indicating potential input terminal thereof, its source connected to said second indicating potential output terminal thereof, and its gate connected to said complementary-value binary bit operand input thereof; said first FET device in each of said cells forming a conductive path between said first indicating potential input terminal and said first indicating potential output terminal and said fourth FET device in the same cell forming a conductive path between said second indicating potential input terminal and said second indicating potential output terminal when said complementary-value binary bit operand input in the same cell is active; said third FET device in each of said cells forming a conductive path between said first indicating potential input terminal and said second indicating potential output terminal and said second FET device in the same cell forming a conductive path between said second indicating potential input terminal and said first indicating potential output terminal when said true-value binary bit operand input in the same cell is active; said first indicating potential input terminal in a first one of said cells in said sequence having a first DC potential continuously applied to it corresponding to a binary one bit value and said second indicating potential input terminal in said first one of said cells having a second DC potential continuously applied to it corresponding to a binary zero bit value said first DC potential being different from said second DC potential; said second indicating potential output terminal in a last one of said cells in said sequence outputting a signal corresponding to said first DC potential in response to an odd number of said cells having their respective true-value binary bit operand input active indicating an odd parity and said second indicating potential output terminal in said last cell outputting a signal corresponding to said second DC potential in response to an even number of said cells having their respective true-value binary bit operand input active indicating an even parity.
Claim 2
Dependent Claim
605 words
A parity circuit for determining whether an odd or even number of binary bits having an even number of binary bits having a value of one, are present, at an n-bit plurality of binary operand bit inputs, comprising: n-stages of sequentially connected steering cells, each said cell including a true-value binary bit operand input and a complementary-value binary bit operand input for one said plurality of operand bit inputs, a first and a second indicating potential input terminals and a first and a second indicating potential output terminals; said first indicating potential input terminal of an i-th cell connected to said first indicating potential output terminal of the next preceding i+1th cell and said second indicating potential input terminal of said i-th cell connected to said second indicating potential output terminal of said next preceding i+1th cell; a first FET device in each said cell having its drain connected to said first indicating potential input terminal thereof, its source connected to said first indicating potential output terminal thereof, and its gate connected to said complementary-value binary bit operand input thereof; a second FET device in each said cell having its drain connected to said second indicating potential input terminal thereof, its source connected to said first indicating potential output terminal thereof, and its gate connected to said true-value binary bit operand input thereof; a third FET device in each said cell having its drain connected to said first indicating potential input terminal thereof, its source connected to said second indicating potential output terminal thereof, and its gate connected to said true-value binary bit operand input thereof; a fourth FET device in each said cell having its drain connected to said second indicating potential input terminal thereof, its source connected to said second indicating potential output terminal thereof, and its gate connected to said complementary-value binary bit operand input thereof; said first FET device in each of said cells forming a conductive path between said first indicating potential input terminal and said first indicating potential output terminal and said fourth FET device in the same cell forming a conductive path between said second indicating potential input terminal and said second indicating potential output terminal when said complementary-value binary bit operand input in the same cell is active; said third FET device in each of said cells forming a conductive path between said first indicating potential input terminal and said second indicating potential output terminal and said second FET device in the same cell forming a conductive path between said second indicating potential input terminal and said first indicating potential output terminal when said true-value binary bit operand input in the same cell is active; said first indicating potential input terminal in a first one of said cells in said sequence having a first DC potential continuously applied to it corresponding to a binary one bit value and said second indicating potential input terminal in said first one of said cells having a second DC potential continuously applied to it corresponding to a binary zero bit value said first DC potential being different from said second DC potential; said second indicating potential output terminal in a last one of said cells in said sequence outputting a signal corresponding to said first DC potential in response to an odd number of said cells having their respective true-value binary bit operand input active indicating an odd parity and said second indicating potential output terminal in said last cell outputting a signal corresponding to said second DC potential in response to an even number of said cells having their respective true-value binary bit operand input active indicating an even parity.
Claim 3
Dependent Claim
121 words
The parity circuit of claim 1, which further comprises: a fifth FET device having its gate connected to the first indicating potential output terminal of said last one of said cells in said sequence, its drain connected to an odd output node and its source connected to said second potential; a sixth FET device having its gate connected to said second indicating potential output in said last one of said cells in said sequence, its drain connected to said first potential and its source connected to said odd output node; said odd output node having said first potential in response to an odd number of said cells having their respective true value binary bit operand input active indicating an odd parity.
Claim 4
Dependent Claim
122 words
The parity circuit of claim 2, which further comprises: a seventh FET device having its gate connected to said second indicating potential output in said last one of said cells in said sequence, having its drain connected to an even output node and its source connected to said second potential; an eighth FET device having its gate connected to said first indicating potential output terminal in said last one of said cells in said sequence, its drain connected to said first potential and its source connected to said even output node; said even output node having said first potential in response to an even number of said cells having their respective true value binary bit operand input active indicating an even parity.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-05-29 | 1987-11-28 | 1988-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-05-29 | 1991-11-28 | 1992-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-05-29 | 1995-11-28 | 1996-05-29 | $7700.00 | Window Closed / Lapsed |