US3846751A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Four-bit parity checker/generator
Assignee: Telex Computer Products Inc
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Filing: 1973-06-12
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Granted: 1974-11-05
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Expires: 1993-06-12
Abstract
Abstract This disclosure described a parity checker/generator which utilizes as its basic central portion, a commercial integrated circuit chip called a data selector/multiplexer. The data selector/multiplexer has provision for eight input terminals three data select terminals and an output terminal. By proper selection of the bits introduced into each of the three data select terminals, one and only one of the eight input terminals is connected to the output terminal. By selectively incrementing the binary number introduced into the data terminals, the eight input terminals can be selectively and sequentially connected to the output. This is the normal use of this device as a multiplexer. In this application one of the data input terminals is connected, with the three data select terminals, as a four input terminal parity checker. Depending on the bits present on the four input terminals the output will be a logic one or zero in accordance with the selected convention, to make an even or odd parity checker.
Inventors
- 👤 A Prieto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:07
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
119 words
A four bit parity checker comprising: a. an eight bit data selector/multiplexer integrated circuit having three input address terminals, eight data input terminals and at least one Q output terminal and including means to connect said eight data terminals into two sets of four each, a first set comprising terminals D1, D2, D4, D7 and the second set comprising terminals D0, D3, D5, D6; b. means to connect three data circuits to said three input address terminals; c. means to connect a fourth data circuit to one of the said two sets of data input terminals; and d. means also to connect said fourth data circuit through inverter means to the other of said two sets of data terminals.
Claim 2
Dependent Claim
119 words
A four bit parity checker comprising: a. an eight bit data selector/multiplexer integrated circuit having three input address terminals, eight data input terminals and at least one Q output terminal and including means to connect said eight data terminals into two sets of four each, a first set comprising terminals D1, D2, D4, D7 and the second set comprising terminals D0, D3, D5, D6; b. means to connect three data circuits to said three input address terminals; c. means to connect a fourth data circuit to one of the said two sets of data input terminals; and d. means also to connect said fourth data circuit through inverter means to the other of said two sets of data terminals.
Claim 3
Dependent Claim
30 words
The parity checker as in claim 1 in which said fourth data circuit is connected to said first set of data terminals, and through said inverter to said second set.
Claim 4
Dependent Claim
12 words
means to connect three data circuits to said three input address terminals;
Claim 5
Dependent Claim
12 words
means to connect three data circuits to said three input address terminals;
Claim 6
Dependent Claim
19 words
means to connect a fourth data circuit to one of the said two sets of data input terminals; and
Claim 7
Dependent Claim
19 words
means to connect a fourth data circuit to one of the said two sets of data input terminals; and
Claim 8
Dependent Claim
20 words
The parity checker as in claim 2 in which the output terminal of said parity checker is said Q terminal.
Claim 9
Dependent Claim
26 words
The parity checker as in claim 2 including an inverted Q terminal, and in which the output terminal of said parity checker is said Q terminal.
Claim 10
Dependent Claim
59 words
means also to connect said fourth data circuit through inverter means to the other of said two sets of data terminals; b. a first exclusive OR gate means having two input terminals connected respectively to the corresponding outputs of said four bit parity checkers; and c. inverter means connected to the output of said first exclusive OR gate means.
Claim 11
Dependent Claim
59 words
means also to connect said fourth data circuit through inverter means to the other of said two sets of data terminals; b. a first exclusive OR gate means having two input terminals connected respectively to the corresponding outputs of said four bit parity checkers; and c. inverter means connected to the output of said first exclusive OR gate means.
Claim 12
Dependent Claim
30 words
The parity checker as in claim 1 in which said fourth data circuit is connected to said second set of data terminal, and through said inverter to said first set.
Claim 13
Dependent Claim
20 words
The parity checker as in claim 5 in which the output terminal of said parity checker is said Q terminal.
Claim 14
Dependent Claim
26 words
The parity checker as in claim 5 including an inverted Q terminal, and in which the output terminal of said parity checker is said Q terminal.
Claim 15
Dependent Claim
14 words
An eight bit parity checker comprising: a. two four bit parity checkers each comrising;
Claim 16
Dependent Claim
14 words
An eight bit parity checker comprising: a. two four bit parity checkers each comrising;
Claim 17
Dependent Claim
25 words
The eight bit parity checker as in claim 8 in which said corresponding outputs are the Q terminals of said two four bit parity checkers.
Claim 18
Dependent Claim
25 words
The eight bit parity checker as in claim 8 in which said corresponding outputs are the Q terminals of said two four bit parity checkers.
Claim 19
Dependent Claim
43 words
The eight bit parity checker as in claim 8 including a second exclusive OR gate meaNs, one input terminal connected to said inverter and the second input terminal connected to the parity channel corresponding to the eight data channels connected to said inputs.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-11-04 | 1978-05-06 | 1978-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-11-04 | 1982-05-06 | 1982-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-11-04 | 1986-05-06 | 1986-11-05 | $7700.00 | Window Closed / Lapsed |