Patent US4451921A successfully refreshed from Google Patents.
US4451921A
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PCM Signal processing circuit
Assignee: Sony Corp
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Filing: 1981-08-04
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Granted: 1984-05-29
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Expires: 2001-08-04
Abstract
Abstract A pulse code modulation signal processing circuit, for example, for an audio recording and reproducing apparatus to be used with a video tape recorder wherein errors occurring in the pulse code modulated signals are detected by serially providing incoming pulse code modulated data words to serially connected shift registers which are, respectively, adapted to store one word. The outputs of the first and third register are added and divided by two and this divided output is added with the inverted output of the second shift register and the results are compared with a reference signal to determine a one or zero. The one indicates that there is an error in one of the words and the zero indicates that there is no error. The ones or zeros from the comparing circuit are stored in three serially connected one bit shift registers which are timed with the data receiving shift registers and if a one occurs in any of the second shift registers an interpolation circuit is utilized to interpolate the output serial connected words from the first three shift registers. When the second shift register does not contain any ones, but contain only zeros, then it is known that the signals in the first three serially connected shift registers are correct.
Inventors
- 👤 Kentaro Odaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:43
CPC Classifications
G; G11; G11B; G11B27/00; G11B27/02; G11B27/031; G11B20/00; G11B20/10; G11B20/18; G11B20/1806; G11B20/1876
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
320 words
A pulse code modulation signal processing circuit for detecting errors in pulse code modulated signal words, the detected errors being used to control an associated interpolation circuit for correcting these errors comprising: a first shift register capable of storing plural data words having a series input terminal, a series output terminal, and plural parallel output terminals, said first shift register receiving at its series input terminal a pulse code modulated signal structured into successive data words, said first shift register series output terminal being connected in series to an input terminal of an interpolation circuit, which subsequently corrects errors in data words outputted from said first shift register upon operation of said interpolation circuit; a detection circuit connected to said plural parallel output terminals of said first shift register for detecting a data error in at least one data word stored in said first shift register by comparing data contained in said stored plural data words in said first shift register by using a linear prediction method, said detection circuit further outputting a discrete signal indicating whether or not an error is present in said one data word in said first shift register; a second shift register connected to the output of said detection circuit having the capacity for storing plural designation bits, each designation bit corresponding to a designated data word in said first shift register, said second shift register receiving said discrete output signal from said detection circuit and shifting one designation bit position each time said discrete output signal is received; a control circuit connected to parallel outputs of said second shift register and to said interpolation circuit, said control circuit turning on said interpolation circuit whenever any one of said plural designation bits stored in said second shift register indicates data word error, and turning off said interpolation circuit whenever none of the plural designation bits stored in said second shift register indicates data word error.
Claim 2
Dependent Claim
320 words
A pulse code modulation signal processing circuit for detecting errors in pulse code modulated signal words, the detected errors being used to control an associated interpolation circuit for correcting these errors comprising: a first shift register capable of storing plural data words having a series input terminal, a series output terminal, and plural parallel output terminals, said first shift register receiving at its series input terminal a pulse code modulated signal structured into successive data words, said first shift register series output terminal being connected in series to an input terminal of an interpolation circuit, which subsequently corrects errors in data words outputted from said first shift register upon operation of said interpolation circuit; a detection circuit connected to said plural parallel output terminals of said first shift register for detecting a data error in at least one data word stored in said first shift register by comparing data contained in said stored plural data words in said first shift register by using a linear prediction method, said detection circuit further outputting a discrete signal indicating whether or not an error is present in said one data word in said first shift register; a second shift register connected to the output of said detection circuit having the capacity for storing plural designation bits, each designation bit corresponding to a designated data word in said first shift register, said second shift register receiving said discrete output signal from said detection circuit and shifting one designation bit position each time said discrete output signal is received; a control circuit connected to parallel outputs of said second shift register and to said interpolation circuit, said control circuit turning on said interpolation circuit whenever any one of said plural designation bits stored in said second shift register indicates data word error, and turning off said interpolation circuit whenever none of the plural designation bits stored in said second shift register indicates data word error.
Claim 3
Dependent Claim
97 words
A pulse code modulation signal processing circuit according to claim 1, wherein said detection circuit includes a prediction circuit for predicting the data value of one data word on the basis of data before and after said one data word and comprises a circuit for calculating the difference between the predicted data value obtained from said prediction circuit and the actual data value and a circuit for determining the absolute value of said difference, and a circuit for comparing said absolute value with a reference value, said discrete error detecting signal being obtained from said comparison circuit.
Claim 4
Dependent Claim
20 words
A pulse code modulation signal processing circuit according to claim 2, wherein said prediction circuit is a mean value circuit.
Claim 5
Dependent Claim
29 words
A pulse code modulation signal processing circuit according to claim 1, wherein said control circuit is a gate circuit which ORs the parallel outputs of said second shift register.
Claim 6
Dependent Claim
46 words
A pulse code modulation signal processing circuit according to claim 1, wherein the number of words n of said first shift register is set to n≧2x when it is predicted that erroneous data will be produced continuously in x words and where n is an integer.
Claim 7
Dependent Claim
38 words
A pulse code modulation signal processing circuit according to claim 1, characterized by further including gate means for disconnecting the output of said detection circuit to said second shift register based on the output of said control circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-05-29 | 1987-11-28 | 1988-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-05-29 | 1991-11-28 | 1992-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-05-29 | 1995-11-28 | 1996-05-29 | $7700.00 | Window Closed / Lapsed |