US4449201A
Expired / Lapsed
US
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Geometric processing system utilizing multiple identical processors
Assignee: Leland Stanford Junior University
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Filing: 1981-04-30
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Granted: 1984-05-15
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Expires: 2001-04-30
Abstract
Abstract A graphic display system uses a plurality of identical processor units each of which is controlled by microcode to perform a particular function in transforming, clipping, and scaling geometric data for presentation on a display. Each processor includes a plurality of function units which can operate independently, in parallel, or in master-slave mode. Each function unit comprises a plurality of one bit slice circuits which can be fabricated using VLSI techniques. Each one bit slice includes a multilevel memory which collectively provide a dispersed stack for the function unit.
Inventors
- 👤 James H. Clark
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 05:59
CPC Classifications
G; G06; G06T; G06T3/00; G06T3/40; F; F02; F02B; F02B75/00; F02B75/02; F02B2075/022; F02B2075/027
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
404 words
A processor for use in a geometric processing system comprising a plurality of identical function units, each of said function units operating on multiple bit data and comprising a plurality of one bit slice circuits each including arithmetic logic means for operating on a bit of said data with each of one bit slice circuit interconnected with like circuits including at least one lower order circuit for operating on a lower order bit an at least one higher order circuit for operating on a higher order bit of said multiple bit data, each of said one bit slice circuits including a multiple level storage means which cooperatively functions as a dispersed data stack for said function unit, each one bit slice circuit comprising a single bit arithmetic logic unit having a first ALU input, a second ALU input, and an ALU output, a first bus for transferring a data bit to said first ALU input, a second bus for transferring a data bit to said second ALU input, a third bus for transferring a data bit from said ALU output, an upshifting register having an input and first and second outputs, said input operably connected to receive a data bit from a lower order circuit and said first output transferring the data bit to said first bus, and said first input operably connected to receive a data bit from said third bus and said second output transferring the data bit to a higher order circuit, a downshifting register having an input and first and second outputs operably connected to receive a data bit from a higher order circuit and transferring the data bit to said second bus, and said first input operably connected to receive a data bit from said third bus and said second output transferring the data bit to a lower order circuit, an accumulator register interconnected between said third bus and said first bus for receiving a data bit from said ALU output and applying said data bit to said first ALU input, an interface register connected to said second bus for transferring a data bit from an input/output bus to said second bus, and a multiple level register interconnected with said second and said third bus for saving and restoring bits for processing, and control means for controlling said function units to cooperatively provide at least a portion of one of the functions including matrix transformations, clipping and scaling functions.
Claim 2
Dependent Claim
404 words
A processor for use in a geometric processing system comprising a plurality of identical function units, each of said function units operating on multiple bit data and comprising a plurality of one bit slice circuits each including arithmetic logic means for operating on a bit of said data with each of one bit slice circuit interconnected with like circuits including at least one lower order circuit for operating on a lower order bit an at least one higher order circuit for operating on a higher order bit of said multiple bit data, each of said one bit slice circuits including a multiple level storage means which cooperatively functions as a dispersed data stack for said function unit, each one bit slice circuit comprising a single bit arithmetic logic unit having a first ALU input, a second ALU input, and an ALU output, a first bus for transferring a data bit to said first ALU input, a second bus for transferring a data bit to said second ALU input, a third bus for transferring a data bit from said ALU output, an upshifting register having an input and first and second outputs, said input operably connected to receive a data bit from a lower order circuit and said first output transferring the data bit to said first bus, and said first input operably connected to receive a data bit from said third bus and said second output transferring the data bit to a higher order circuit, a downshifting register having an input and first and second outputs operably connected to receive a data bit from a higher order circuit and transferring the data bit to said second bus, and said first input operably connected to receive a data bit from said third bus and said second output transferring the data bit to a lower order circuit, an accumulator register interconnected between said third bus and said first bus for receiving a data bit from said ALU output and applying said data bit to said first ALU input, an interface register connected to said second bus for transferring a data bit from an input/output bus to said second bus, and a multiple level register interconnected with said second and said third bus for saving and restoring bits for processing, and control means for controlling said function units to cooperatively provide at least a portion of one of the functions including matrix transformations, clipping and scaling functions.
Claim 3
Dependent Claim
235 words
A geometric processing system for receiving geometric data, transforming coordinates of said geometric data, clipping said transformed data for selective presentation on a viewing screen, and scaling said data for presentation on said viewing screen, comprising a first plurality of processor units for transforming coordinates of said geometric data, a second plurality of processors operably connected with said first plurality of processor units for receiving and clipping transformed coordinates for selective viewing of the geometric data, and a third plurality of processorss operably connected with said second plurality of processor units for scaling said clipped data, each of said processor units comprising a plurality of function units, each of said function units operating on multiple bit data and comprising a plurality of one bit slice circuits each including arithmetic logic means for operating on a bit of said data with each of one bit slice circuit interconnected with like circuits including at least one lower order circuit for operating on a lower order bit and at least one higher order circuit for operating on a higher order bit of said multiple bit data, each of said one bit slice circuits including a multiple level storage means which cooperatively function as a dispersed data stack for said function unit, and control means for controlling said function units to cooperatively provide at least a portion of one of the functions including matrix transformations, clipping, and scaling functions.
Claim 4
Dependent Claim
235 words
A geometric processing system for receiving geometric data, transforming coordinates of said geometric data, clipping said transformed data for selective presentation on a viewing screen, and scaling said data for presentation on said viewing screen, comprising a first plurality of processor units for transforming coordinates of said geometric data, a second plurality of processors operably connected with said first plurality of processor units for receiving and clipping transformed coordinates for selective viewing of the geometric data, and a third plurality of processorss operably connected with said second plurality of processor units for scaling said clipped data, each of said processor units comprising a plurality of function units, each of said function units operating on multiple bit data and comprising a plurality of one bit slice circuits each including arithmetic logic means for operating on a bit of said data with each of one bit slice circuit interconnected with like circuits including at least one lower order circuit for operating on a lower order bit and at least one higher order circuit for operating on a higher order bit of said multiple bit data, each of said one bit slice circuits including a multiple level storage means which cooperatively function as a dispersed data stack for said function unit, and control means for controlling said function units to cooperatively provide at least a portion of one of the functions including matrix transformations, clipping, and scaling functions.
Claim 5
Dependent Claim
270 words
A geometric processing system as defined by claim 2 wherein each one bit slice circuit comprises a single bit arithmetic logic unit having a first ALU input, a second ALU input, and an ALU output, a first bus for transferring a data bit to said first ALU input, a second bus for transferring a data bit to said second ALU input, a third bus for transferring a data bit from said ALU output, an upshifting register having an input and first and second outputs, said input operably connected to receive a data bit from a lower order circuit and said first output transferring the data bit to said first bus, and said first input operably connected to receive a data bit from said third bus and said second output transferring the data bit to a higher order circuit, a downshifting register having an input and, first and second outputs operably connected to receive a data bit from a higher order circuit and transferring the data bit to said second bus, and said first input operably connected to receive a data bit from said third bus and said second output transferring the data bit to a lower order circuit, an accumulator register interconnected between said third bus and said first bus for receiving a data bit from said ALU output and applying said data bit to said first ALU input, an interface register connected to said second bus for transferring a data bit from an input/output bus to said second bus, and a multiple level register interconnected with said second and said third bus for saving and restoring bits for processing.
Claim 6
Dependent Claim
332 words
A processor for use in a geometric processing system comprising a plurality of identical floating point function units (W, X, Y, Z), each function unit including a first portion for operating on the mantissa of a floating point number and a second portion for operating on the characteristic of a floating point number, each portion of a function unit including a plurality of identical circuits for operating on multiple bit data, each circuit comprising an arithmetic logic unit having a first ALU input, a second ALU input, and an ALU output, a first bus for transferring data to said first ALU input, a second bus for transferring data to said second ALU input, a third bus for transferring data from said ALU output, an upshifting register having an input and first and second outputs, said input operably connected to receive data from a lower order circuit and said first output transferring the data to said first bus, and said input operably connected to receive data from said third bus and said second output transferring the databit to a higher order circuit, a downshifting register having an input and first and second outputs, said input operably connected to receive data from a higher order circuit and said first output transferring the data to said second bus, and said input operably connected to receive data from said third bus and said second output transferring the data to a lower order circuit, an accumulator register interconnected between said third bus and said first bus for receiving data from said ALU output and applying said data to said first ALU input, an interface register connected to said second bus for transferring data from an input/output bus to said second bus, a multiple level register interconnected with said second and said third bus for saving and restoring data for processing, and control means for controlling said function units to cooperatively provide at least a portion of one of the functions including matrix transformations, clipping, and scaling functions.
Claim 7
Dependent Claim
332 words
A processor for use in a geometric processing system comprising a plurality of identical floating point function units (W, X, Y, Z), each function unit including a first portion for operating on the mantissa of a floating point number and a second portion for operating on the characteristic of a floating point number, each portion of a function unit including a plurality of identical circuits for operating on multiple bit data, each circuit comprising an arithmetic logic unit having a first ALU input, a second ALU input, and an ALU output, a first bus for transferring data to said first ALU input, a second bus for transferring data to said second ALU input, a third bus for transferring data from said ALU output, an upshifting register having an input and first and second outputs, said input operably connected to receive data from a lower order circuit and said first output transferring the data to said first bus, and said input operably connected to receive data from said third bus and said second output transferring the databit to a higher order circuit, a downshifting register having an input and first and second outputs, said input operably connected to receive data from a higher order circuit and said first output transferring the data to said second bus, and said input operably connected to receive data from said third bus and said second output transferring the data to a lower order circuit, an accumulator register interconnected between said third bus and said first bus for receiving data from said ALU output and applying said data to said first ALU input, an interface register connected to said second bus for transferring data from an input/output bus to said second bus, a multiple level register interconnected with said second and said third bus for saving and restoring data for processing, and control means for controlling said function units to cooperatively provide at least a portion of one of the functions including matrix transformations, clipping, and scaling functions.
Claim 8
Dependent Claim
165 words
A geometric processing system having multiple identical pipelined processors for receiving geometric data, transforming coordinates of said geometric data, clipping said transformed data, and scaling said clipped data, said system comprising a first plurality of serially connected processors for receiving and transforming coordinates of said geometric data, a second plurality of serially connected processors serially connected with said first plurality of serially connected processors for receiving and clipping transformed coordinates, and a third plurality of serially connected processors serially connected with said second plurality of serially connected processors for scaling said clipped data, each of said processors comprising a plurality of function units (W, X, Y, Z), each function unit including a first portion for operating on the mantissa of a floating point number and a second portion for operating on the characteristic of a floating point number, and control means for controlling said function units to cooperatively provide at least a portion of one of the functions including matrix transformations, clipping, and scaling functions.
Claim 9
Dependent Claim
165 words
A geometric processing system having multiple identical pipelined processors for receiving geometric data, transforming coordinates of said geometric data, clipping said transformed data, and scaling said clipped data, said system comprising a first plurality of serially connected processors for receiving and transforming coordinates of said geometric data, a second plurality of serially connected processors serially connected with said first plurality of serially connected processors for receiving and clipping transformed coordinates, and a third plurality of serially connected processors serially connected with said second plurality of serially connected processors for scaling said clipped data, each of said processors comprising a plurality of function units (W, X, Y, Z), each function unit including a first portion for operating on the mantissa of a floating point number and a second portion for operating on the characteristic of a floating point number, and control means for controlling said function units to cooperatively provide at least a portion of one of the functions including matrix transformations, clipping, and scaling functions.
Claim 10
Dependent Claim
262 words
The system as defined by claim 5 wherein each portion of a function unit includes a plurality of identical circuits for operating on multiple bit data, each circuit comprising an arithmetic logic unit having a first ALU input, a second ALU input, and an ALU output a first bus for transferring data to said first ALU input, a second bus for transferring data to said second ALU input, a third bus for transferring data from said ALU output, an upshifting register having an input and first and second outputs, said input operably connected to receive data from a lower order circuit and said first output transferring the data to said first bus, and said input operably connected to receive data from said third bus and said second output transferring the data bit to a higher order circuit, a downshifting register having an input and first and second outputs, said input operably connected to receive data from a higher order circuit and said first output transferring the data to said second bus, and said input operably connected to receive data from said third bus and said second output transferring the data to a lower order circuit, an accumulator register interconnected between said third bus and said first bus for receiving data from said ALU output and applying said data to said first ALU input, an interface register connected to said second bus for transferring data from an input/output bus to said second bus, and a multiple level register interconnected with said second and said third bus for saving and restoring data for processing.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-05-15 | 1987-11-14 | 1988-05-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-05-15 | 1991-11-14 | 1992-05-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-05-15 | 1995-11-14 | 1996-05-15 | $7700.00 | Window Closed / Lapsed |