US4217657A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Floating point arithmetic control
Assignee: Honeywell Inc
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Filing: 1978-10-18
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Granted: 1980-08-12
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Expires: 1998-10-18
Abstract
Abstract An improved means and method for accomplishing floating point calculations in computational apparatus includes a primary microprocessor and a secondary microprocessor each with its own control ROM. The normal or fixed point calculations are handled by the primary microprocessor under the control of a first segment of the associated control ROM. When a floating point calculation is called for, a second segment of that ROM is addressed. The addressing of the second segment of the first ROM also effects the coincident addressing of the ROM of the secondary microprocessor. For floating point calculations, the exponent portion of the numbers being manipulated is handled in the primary microprocessor. Simultaneously therewith, the mantissa portion of the numbers being manipulated are handled in the secondary microprocessor under the control of its associated control ROM. The resultant calculations are recombined in the primary microprocessor to produce a complete solution for the floating point calculation.
Inventors
- 👤 Robert J. Handly
- 👤 Robert H. Douglas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:24
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/483
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
225 words
Computational apparatus for effecting floating point calculations comprising: a first microprocessor including a first arithmetic logic unit and a first control ROM; said first control ROM including a first segment having a first number of addressable words for the control of said first microprocessor during fixed point calculations, and a second segment having a second number of addressable words for the control of said first microprocessor during floating point calculations; means for addressing said first segment of said first control ROM for said fixed point calculations and for addressing said second segment of said ROM for said floating point calculations; a second microprocessor having a second arithmetic logic unit and a second control ROM; said second control ROM having a number of addressable control words which corresponds to the number of control words in said second segment of said first control ROM for the control of said second microprocessor during said floating point calculations; and means for addressing said second control ROM coincidently with the addressing of said second segment of said first control ROM; interconnection means between said first and second microprocessor so interconnecting said first and second microprocessors that a first portion of said values being manipulated in a floating point calculation are manipulated by said first microprocessor simultaneously with the manipulation of a second portion of said values by said second microprocessor.
Claim 2
Dependent Claim
225 words
Computational apparatus for effecting floating point calculations comprising: a first microprocessor including a first arithmetic logic unit and a first control ROM; said first control ROM including a first segment having a first number of addressable words for the control of said first microprocessor during fixed point calculations, and a second segment having a second number of addressable words for the control of said first microprocessor during floating point calculations; means for addressing said first segment of said first control ROM for said fixed point calculations and for addressing said second segment of said ROM for said floating point calculations; a second microprocessor having a second arithmetic logic unit and a second control ROM; said second control ROM having a number of addressable control words which corresponds to the number of control words in said second segment of said first control ROM for the control of said second microprocessor during said floating point calculations; and means for addressing said second control ROM coincidently with the addressing of said second segment of said first control ROM; interconnection means between said first and second microprocessor so interconnecting said first and second microprocessors that a first portion of said values being manipulated in a floating point calculation are manipulated by said first microprocessor simultaneously with the manipulation of a second portion of said values by said second microprocessor.
Claim 3
Dependent Claim
49 words
The computational apparatus as set forth in claim 1 wherein, with said values being expressed in scientific notation, said first portion of said values manipulated by said first microprocessor comprises the exponent portion and said second portion of said values manipulated by said second microprocessor comprises the mantissa portion.
Claim 4
Dependent Claim
54 words
The computational apparatus as set forth in claim 2 wherein said second microprocessor has an output means connected to an input means of said first microprocessor to return the manipulated mantissa portion of said values to said first microprocessor for recombination with the manipulated exponent portion of said values to provide a composite result.
Claim 5
Dependent Claim
48 words
The computational apparatus as set forth in claim 2 wherein the interconnection between said first and second microprocessors includes an output connection from said first arithmetic logic unit to the input of said second microprocessor for the transfer of mantissa values to said second microprocessor for manipulation thereby.
Claim 6
Dependent Claim
48 words
The computational apparatus as set forth in claim 4 wherein interconnection means are provided between said means for addressing first control ROM and said means for addressing second control ROM to effect the addressing of said second ROM whenever said second segment of said first ROM is addressed.
Claim 7
Independent Claim
73 words
The method of effecting floating point calculations in a computational apparatus having a first and a second microprocessor unit, said method comprising: manipulating the exponent portion of values in said first microprocessor unit, simultaneously therewith, manipulating the mantissa portion of the values in said second microprocessor unit, and recombining the manipulated maintissa portion from said second microprocessor unit with the manipulated exponent portion in said first microprocessor unit to provide a composite result.
Claim 8
Independent Claim
73 words
The method of effecting floating point calculations in a computational apparatus having a first and a second microprocessor unit, said method comprising: manipulating the exponent portion of values in said first microprocessor unit, simultaneously therewith, manipulating the mantissa portion of the values in said second microprocessor unit, and recombining the manipulated maintissa portion from said second microprocessor unit with the manipulated exponent portion in said first microprocessor unit to provide a composite result.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-08-12 | 1984-02-11 | 1984-08-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-08-12 | 1988-02-11 | 1988-08-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-08-12 | 1992-02-11 | 1992-08-12 | $7700.00 | Window Closed / Lapsed |