Implementation of instruction for a branch which can cross one page boundary

Claim 2

In a data processing system employing a program counter (PC), and a memory divided into pages each containing 2 N memory locations, and in which each of the memory location addresses comprises two bytes, an upper order byte, and a lower order byte, with each byte comprising N bits, an improved method for executing a branch instruction directing a branch from one memory address in one page of the memory to a second memory address in a location not beyond an adjacent page of the memory, but independent of whether the branch crosses a page boundary in the memory, and comprising the steps of: determining if the binary value V1 represented by the (N-1) least significant bits (LSB's) of the lower order byte of the branch address is greater than the binary value V2 represented by the (N-1) LSB's of the lower order byte of the address to which the PC is pointing (the PC address); determining if PC N≠BR N where PC N is the most significant bit of the lower order byte of the PC address and BR N is the most significant bit of the lower order byte of the branch address; incrementing by 1 the upper order byte of the PC address if V1<V2, PC N=1, and PC N≠BR N; decrementing by 1 the upper order byte of the PC address if V1>V2, PC N=0, and PC N≠BR N; and replacing the lower order byte of the PC address with the lower order byte of the branch address.

Claim 3

In a data processing system employing a program counter (PC), and a memory divided into pages each containing 2 N memory locations, and in which each of the memory location addresses comprises two bytes, an upper order byte and a lower order byte, with each byte comprising N bits, a structure for executing a branch instruction containing a branch address and directing a branch from one memory address in one page of the memory to a second memory address at a location not beyond an adjacent page of the memory, but independent of whether a page boundary in said memory is crossed during said branch, and comprising: first logic means responsive to the binary value V2 represented by the (N-1) least significant bits (LSB's) of the lower order byte of the address to which the PC is pointing (the PC address), and the binary value V1 represented by the (N-1) LSB's of the lower order byte of said branch address to produce a first output signal if V1<V2 and a second output signal if V1>V2; second logic means responsive to the most significant bit (MSB) PC N of the lower order byte of the PC address and the MSB BR N of the lower order byte of said branch address to produce a third output signal if PC N≠BR N; third logic means responsive to the condition PC N=1, and to said first and third output signals to provide a fourth output signal for incrementing said upper order byte of said PC address by one; fourth logic means responsive to the condition PC N=0, and to said second and third output signals to provide a fifth output signal for decrementing said upper order byte of said PC address by one; and fifth logic means for replacing the lower order byte of the PC address with the lower order byte of the branch address after the execution of said branch instruction.

Claim 4

In a data processing system employing a program counter (PC), and a memory divided into pages each containing 2 N memory locations, and in which each of the memory location addresses comprises two bytes, an upper order byte and a lower order byte, with each byte comprising N bits, a structure for executing a branch instruction containing a branch address and directing a branch from one memory address in one page of the memory to a second memory address at a location not beyond an adjacent page of the memory, but independent of whether a page boundary in said memory is crossed during said branch, and comprising: first logic means responsive to the binary value V2 represented by the (N-1) least significant bits (LSB's) of the lower order byte of the address to which the PC is pointing (the PC address), and the binary value V1 represented by the (N-1) LSB's of the lower order byte of said branch address to produce a first output signal if V1<V2 and a second output signal if V1>V2; second logic means responsive to the most significant bit (MSB) PC N of the lower order byte of the PC address and the MSB BR N of the lower order byte of said branch address to produce a third output signal if PC N≠BR N; third logic means responsive to the condition PC N=1, and to said first and third output signals to provide a fourth output signal for incrementing said upper order byte of said PC address by one; fourth logic means responsive to the condition PC N=0, and to said second and third output signals to provide a fifth output signal for decrementing said upper order byte of said PC address by one; and fifth logic means for replacing the lower order byte of the PC address with the lower order byte of the branch address after the execution of said branch instruction.

Claim 5

In a data processor system employing a program counter (PC), and a memory divided into pages each containing 2 N memory locations, and in which each of the memory location addresses comprises two bytes, an upper order byte and a lower order byte, with each byte comprising N bits, a structure for executing a branch instruction containing a branch address and directing a branch from one memory address in one page of the memory to a second memory address at a location not beyond a adjacent page of the memory, but independent of whether an adjacent page boundary is crossed during said branch and comprising: first logic means responsive to the binary value V2 represented by the (N-1) least significant bits (LSB's) of the lower order byte of the address to which the PC is pointing (the PC address) and the binary value V1 represented by the (N-1) LSB's of the lower order byte of said branch (BR) address to produce a first output signal indicating which of V1 and V2 is the larger; and second logic means responsive to the conditions PC N≠BR N, PC N=1, and V1<V2 to generate a first signal indicating the incrementing of the upper order byte of the PC address, and further responsive to the conditions PC N≠BR N, PC N=0 and V1>V2 to generate a second signal indicating the decrementing of the upper order byte of the PC address, where PC N and BR N are the most significant bit of the lower order byte of the PC address and the lower order byte of said branch address, respectively.

Claim 6

In a data processor system employing a program counter (PC), and a memory divided into pages each containing 2 N memory locations, and in which each of the memory location addresses comprises two bytes, an upper order byte and a lower order byte, with each byte comprising N bits, a structure for executing a branch instruction containing a branch address and directing a branch from one memory address in one page of the memory to a second memory address at a location not beyond a adjacent page of the memory, but independent of whether an adjacent page boundary is crossed during said branch and comprising: first logic means responsive to the binary value V2 represented by the (N-1) least significant bits (LSB's) of the lower order byte of the address to which the PC is pointing (the PC address) and the binary value V1 represented by the (N-1) LSB's of the lower order byte of said branch (BR) address to produce a first output signal indicating which of V1 and V2 is the larger; and second logic means responsive to the conditions PC N≠BR N, PC N=1, and V1<V2 to generate a first signal indicating the incrementing of the upper order byte of the PC address, and further responsive to the conditions PC N≠BR N, PC N=0 and V1>V2 to generate a second signal indicating the decrementing of the upper order byte of the PC address, where PC N and BR N are the most significant bit of the lower order byte of the PC address and the lower order byte of said branch address, respectively.