Actuated digital pretimed traffic controller

Claim 2

In a digital pretimed traffic controller of the type used to control traffic signals at an intersection during a selected signal cycle, said controller including a central processing unit, a read only memory means for storing the executive program for said controller and a plurality of programmed solid state camshaft simulating signal plans each having a number of distinct intervals to be processed in sequence during a cycle of said controller, a random access read/write memory means for storing a rotary dial simulating timing plan having stored duration times for each of said distinct intervals of each of said signal plans stored in said read only memory means, external cycle select means for activating one of said signal plans and one of said timing plans for processing by said controller in accordance with said stored executive program, and interfacing means for controlling the condition of said traffic signals in accordance with the selected cycle being processed by said controller, the improvement comprising: detector means for directing a demand signal to said controller, means for providing a plurality of different interval sequences in a selected portion of the selected cycle being processed and means for selecting one of said interval sequences in response to said demand signal.

Claim 3

The improvement as defined in claim 1 wherein said given cycle has an initial portion with intervals to be processed before said selected sequence of intervals.

Claim 4

The improvement as defined in claim 2 wherein the summation of the duration time of said initial intervals and the duration time of said selected sequence of intervals has a constant cycle length time.

Claim 5

The improvement as defined in claim 1 wherein said selected cycles each have the same cycle length time.

Claim 6

The improvement as defined in claim 1 wherein said signal plan stored in said read only memory means includes minimum times stored for each interval.

Claim 7

The improvement as defined in claim 1 including means for receiving a preemption signal and means responsive to said preemption signal for shifting from one signal plan to another signal plan.

Claim 8

The improvement as defined in claim 6 including means for delaying said signal plan shift a predetermined time.

Claim 9

The improvement as defined in claim 6 including means for preventing said signal plan shift during certain portions of said signal plan.

Claim 10

The improvement as defined in claim 1 including means for setting a cycle length time in a given timing plan, means for comparing the summation of the distinct intervals in said given timing plan with said set cycle length and means for creating a signal when said summation is different from said set cycle length time of said given timing plan.

Claim 11

In a digital pretimed traffic controller of the type used to control traffic signals at an intersection during a signal cycle, said controller including a central processing unit, a read only memory means for storing the executive program for said controller and a plurality of programmed solid state camshaft simulating signal plans each having a number of distinct intervals to be processed in sequence during a cycle of said controller, a random access read/write memory means for storing a rotary dial simulating timing plan having stored duration times for each of said distinct intervals of each of said signal plans stored in said read only memory means, external cycle select means for activating one of said signal plans and one of said timing plans for processing by said controller in accordance with said stored executive program, and interfacing means for controlling the condition of said traffic signals in accordance with the selected cycle being processed by said controller, the improvement comprising: means for adjusting the cycle length time of a selected cycle, means for individually setting the time duration of each individual interval in said selected cycle and means for preventing processing of said selected cycle if said cycle length is different in time from the summation of the duration of said intervals of said selected cycle.

Claim 12

In a digital pretimed traffic controller of the type used to control traffic signals at an intersection during a signal cycle, said controller including a central processing unit, a read only memory means for storing the executive program for said controller and a plurality of programmed solid state camshaft simulating signal plans each having a number of distinct intervals to be processed in sequence during a cycle of said controller, a random access read/write memory means for storing a rotary dial simulating timing plan having stored duration times for each of said distinct intervals of each of said signal plans stored in said read only memory means, external cycle select means for activating one of said signal plans and one of said timing plans for processing by said controller in accordance with said stored executive program, and interfacing means for controlling the condition of said traffic signals in accordance with the selected cycle being processed by said controller, the improvement comprising: means for adjusting the cycle length time of a selected cycle, means for individually setting the time duration of each individual interval in said selected cycle and means for preventing processing of said selected cycle if said cycle length is different in time from the summation of the duration of said intervals of said selected cycle.

Claim 13

In a digital pretimed traffic controller of the type having a central processing unit, a read only memory means for storing the executive program for said controller and a plurality of programmed solid state camshaft simulating signal plans each having a number of distinct intervals to be processed in sequence during a cycle of said controller, a random access read/write memory means for storing a rotary dial simulating timing plan having stored duration times for each of said distinct intervals of each of said signal plans stored in said read only memory means, external cycle select means for activating one of said signal plans and one of said timing plans for processing by said controller in accordance with said stored executive program, and interfacing means for controlling the condition of said traffic signals in accordance with the selected cycle being processed by said controller, the improvement comprising: a means for storing a digital interval advance signal; first converting means for converting said digital advance signal into an alternating current advance signal; conductor means external of said controller for directing said alternating current advance signal to a manually operating switch having an automatic interval advance position; second converting means for converting said alternating current advance signal into a digital advance signal for use by said controller; and means for directing said alternating current advance signal from said first converting means to said second converting means when said switch is shifted into said automatic interval advance position.

Claim 14

In a digital pretimed traffic controller of the type having a central processing unit, a read only memory means for storing the executive program for said controller and a plurality of programmed solid state camshaft simulating signal plans each having a number of distinct intervals to be processed in sequence during a cycle of said controller, a random access read/write memory means for storing a rotary dial simulating timing plan having stored duration times for each of said distinct intervals of each of said signal plans stored in said read only memory means, external cycle select means for activating one of said signal plans and one of said timing plans for processing by said controller in accordance with said stored executive program, and interfacing means for controlling the condition of said traffic signals in accordance with the selected cycle being processed by said controller, the improvement comprising: a means for storing a digital interval advance signal; first converting means for converting said digital advance signal into an alternating current advance signal; conductor means external of said controller for directing said alternating current advance signal to a manually operating switch having an automatic interval advance position; second converting means for converting said alternating current advance signal into a digital advance signal for use by said controller; and means for directing said alternating current advance signal from said first converting means to said second converting means when said switch is shifted into said automatic interval advance position.