Non-inverting non-volatile dynamic RAM cell

Claim 2

A memory cell comprising; a semiconductor substrate having a given type conductivity, a floating gate and a conductive plate insulated from said substrate, a control electrode, said floating gate being interposed between said control electrode and said substrate, means for applying reference voltages to said plate and control electrode to produce first and second contiguous regions in said substrate of opposite conductivity type to that of said given type conductivity, said plate and said first region forming a storage capacitor and said floating gate and said second region forming a first capacitor, a voltage divider circuit having serially-connected said first capacitor and a second capacitor including said floating gate connected to the common point between said first and second capacitors, said voltage divider circuit being disposed between said control electrode and said second opposite conductivity type region, said second capacitor being disposed between said floating gate and said control electrode, and said second capacitor including a first enhanced conduction insulator, an input/output line, and a transfer device disposed between said second opposite conductivity type region and said input/output line.

Claim 3

A memory cell as set forth in claim 1 wherein said first capacitor has a capacitance value substantially greater than that of said second capacitor.

Claim 4

A memory cell as set forth in claim 1 wherein said second capacitor further includes a second enhanced conduction insulator and a given insulating layer disposed between said first and second insulators.

Claim 5

A memory cell as set forth in claim 1 wherein said reference voltages applying means applies a first voltage to said plate having a given magnitude during one period of time and a second voltage having a magnitude substantially higher than that of said given magnitude during another period of time.

Claim 6

A memory cell as set forth in claim 4 wherein said transfer device is a transistor and said input/output line is a bit/sense line.

Claim 7

A memory cell as set forth in claim 5 wherein said transistor is a field effect transistor and said first capacitor has a capacitance value substantially greater than that of said second capacitor.

Claim 8

A memory cell as set forth in claim 6 wherein said second capacitor further includes a second enhanced conduction insulator and a given insulating layer disposed between said first and second insulators.

Claim 9

A memory cell as set forth in claim 7 wherein said reference voltages applying means applies a first voltage to said control electrode having a given magnitude during said one period of time and a second voltage having a magnitude substantially lower than that of the given magnitude of said second reference voltage during said another period of time.

Claim 10

A memory cell as set forth in claim 7 wherein said given insulating layer includes a silicon dioxide layer and each of said first and second enhanced conduction insulators includes a silicon-rich silicon dioxide layer.

Claim 11

A non-volatile dynamic random access memory cell comprising; a semiconductor substrate, storage capacitors having a plate and a floating gate insulated from a given surface area of said substrate, said given area having first and second contiguous portions, said floating gate and said first portion forming a first capacitor and said plate and said second portion forming a second capacitor, means for applying a first reference voltage to said plate for varying the capacitance of said second capacitor, said first reference voltage having a first magnitude during one period of time and a second magnitude substantially smaller than said first magnitude during another period of time, a control electrode, said floating gate being interposed between said control electrode and said substrate, means for applying a second reference voltage to said control electrode for varying the capacitance of said first capacitor, said second reference voltage having a first magnitude during said one period of time and a second magnitude substantially greater than said first magnitude of said second reference voltage during said another period of time so as to transfer charge from said second capacitor to said first capacitor and to selectively decouple said first capacitor from said second capacitor, a voltage divider circuit having serially-connected said first capacitor and a third capacitor including said floating gate connected to the common point between said first and third capacitors, said voltage divider circuit being disposed between said control electrode and the first portion of the given surface area of said substrate, said third capacitor being disposed between said floating gate and said control electrode and including an enhanced conduction insulator, a bit/sense line disposed in said substrate, and a field effect transistor disposed between said bit/sense line and the given surface area of said substrate.

Claim 12

A non-volatile dynamic random access memory cell comprising; a semiconductor substrate, storage capacitors having a plate and a floating gate insulated from a given surface area of said substrate, said given area having first and second contiguous portions, said floating gate and said first portion forming a first capacitor and said plate and said second portion forming a second capacitor, means for applying a first reference voltage to said plate for varying the capacitance of said second capacitor, said first reference voltage having a first magnitude during one period of time and a second magnitude substantially smaller than said first magnitude during another period of time, a control electrode, said floating gate being interposed between said control electrode and said substrate, means for applying a second reference voltage to said control electrode for varying the capacitance of said first capacitor, said second reference voltage having a first magnitude during said one period of time and a second magnitude substantially greater than said first magnitude of said second reference voltage during said another period of time so as to transfer charge from said second capacitor to said first capacitor and to selectively decouple said first capacitor from said second capacitor, a voltage divider circuit having serially-connected said first capacitor and a third capacitor including said floating gate connected to the common point between said first and third capacitors, said voltage divider circuit being disposed between said control electrode and the first portion of the given surface area of said substrate, said third capacitor being disposed between said floating gate and said control electrode and including an enhanced conduction insulator, a bit/sense line disposed in said substrate, and a field effect transistor disposed between said bit/sense line and the given surface area of said substrate.

Claim 13

A non-volatile dynamic random access memory, cell as set forth in claim 10 wherein said third capacitor has a capacitance value substantially less than that of said first capacitor.

Claim 14

A non-volatile dynamic random access memory cell as set forth in claim 10 wherein said third capacitor further includes a layer of silicon dioxide and first and second layers of silicon-rich silicon dioxide disposed on opposite sides of said layer of silicon dioxide.