Patent US4446382A successfully refreshed from Google Patents.
US4446382A
Expired / Lapsed
US
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Arrangement to time separate bidirectional current flow
Assignee: Hewlett Packard Development Co LP
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Filing: 1982-02-24
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Granted: 1984-05-01
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Expires: 2002-02-24
Abstract
Abstract The present disclosure describes a circuit arrangement wherein a clock signal generator generates two sets of time-period, separated enable signals and wherein there is controllable first direction current flow circuitry and controllable second direction current flow circuitry. One set of said enable signals is connected to said first circuitry to cause current flow in a first direction during a first period of time while the other set of said enable signals is connected to said second circuitry to cause current flow in a second direction during a second period of time which is separated from said first period by a predetermined period. The arrangement insures that the circuitry will not attempt to drive current in both directions at the same time.
Inventors
- 👤 Russell L. Moore
- 👤 David J. Schanin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:27
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/66
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
353 words
A circuit arrangement for driving electrical current signals, to and from, between a first and a second circuit, wherein said circuits are interconnected by a tri state bus device, comprising in combination: clock signal generating means formed to generate first enable signals and second enable signals, each of which types of enable signals is a gate-like type, and formed to so generate said signals (1) such that the end of any of said first enable signals occurs a predetermined time period before the beginning of a subsequent one of said second enable signals and (2) such that the end of any of said second enable signal occurs a predetermined time period before the beginning of a subsequent one of said first enable signals; first and second controllable current flow means each having a control element and disposed to be connected to each other through said tri state bus device to conduct current in a first direction in response to a first enable signal being applied to the respective control elements of each; third and fourth controllable current flow means, each having a control element and disposed to be connected to each other through said tri state bus device to conduct current in a second direction in response to a second enable signal being applied to the respective control element of each; first control circuit means connected to said clock signal generating means to receive said first enable signals and further connected to the respective control elements of said first and second controllable current flow means to cause current to be conducted therethrough during the presence of said first enable signal; and second control circuit means connected to said clock signal generating means to receive said second enable signals and further connected to the respective control elements of said third and fourth controllable current flow means to cause current to be conducted therethrough during the presence of said second enable signal, whereby the time period for current flow in said first direction is separated from the time period for current flow in said second direction, and vice versa, by said predetermined period of time.
Claim 2
Dependent Claim
353 words
A circuit arrangement for driving electrical current signals, to and from, between a first and a second circuit, wherein said circuits are interconnected by a tri state bus device, comprising in combination: clock signal generating means formed to generate first enable signals and second enable signals, each of which types of enable signals is a gate-like type, and formed to so generate said signals (1) such that the end of any of said first enable signals occurs a predetermined time period before the beginning of a subsequent one of said second enable signals and (2) such that the end of any of said second enable signal occurs a predetermined time period before the beginning of a subsequent one of said first enable signals; first and second controllable current flow means each having a control element and disposed to be connected to each other through said tri state bus device to conduct current in a first direction in response to a first enable signal being applied to the respective control elements of each; third and fourth controllable current flow means, each having a control element and disposed to be connected to each other through said tri state bus device to conduct current in a second direction in response to a second enable signal being applied to the respective control element of each; first control circuit means connected to said clock signal generating means to receive said first enable signals and further connected to the respective control elements of said first and second controllable current flow means to cause current to be conducted therethrough during the presence of said first enable signal; and second control circuit means connected to said clock signal generating means to receive said second enable signals and further connected to the respective control elements of said third and fourth controllable current flow means to cause current to be conducted therethrough during the presence of said second enable signal, whereby the time period for current flow in said first direction is separated from the time period for current flow in said second direction, and vice versa, by said predetermined period of time.
Claim 3
Dependent Claim
62 words
A circuit arrangement for driving electrical current signals according to claim 1 wherein said first control circuit means includes a pair of buffers connected between said clock signal generating means and said second controllable current flow means and wherein said second control circuit means includes a pair of buffers connected between said clock signal generating means and said fourth controllable current means.
Claim 4
Dependent Claim
71 words
A circuit arrangement for driving electrical current signals according to claim 2 wherein said first control circuit means includes a coincident signal device connected between said second controllable current flow means and the closest one of said two buffers connected thereto and wherein said second control circuit means includes a coincident circuit device connected between said fourth controllable current flow means and the closest one of said two buffers connected thereto.
Claim 5
Dependent Claim
95 words
A circuit arrangement for driving electrical current signals according to claim 3 wherein said first and third controllable current flow means are part of a master circuit arrangement and wherein second and fourth controllable current flow means are part of a slave circuit arrangement and wherein the coincident signal device, connected to said second controllable current flow means and the coincident signal device connected to said fourth controllable current flow means, each has a select input thereto, which when activated selects the slave circuit arrangement to which data will flow from the master circuit arrangement.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-05-01 | 1987-10-31 | 1988-05-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-05-01 | 1991-10-31 | 1992-05-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-05-01 | 1995-10-31 | 1996-05-01 | $7700.00 | Window Closed / Lapsed |