Protection circuit for memory programming system

Claim 2

A protection circuit for an apparatus for generating a high level, controlled risetime, write-erase signal to an electrically erasable programmable read-only memory (E 2 PROM), said signal generating apparatus including means for coupling first and second power supplies thereto, said first and second supplies providing, when operational, first and second potentials, respectively, where said second potential is substantially greater than said first potential, said signal generating apparatus responsive to one voltage level at the input thereof for generating said high level signal and responsive to a different voltage level for providing no output therefrom, said protection circuit inhibiting the generation of said high level signal whenever the potential provided from said first supply drops below the level of a third potential, less than said first potential, while said second supply is operational, said protection circuit comprising: means coupled to said second supply for providing said third potential; means coupled between said second supply and reference ground for comparing the voltage level of said first supply with said third potential, said comparing means generating a control signal when the voltage level of said first supply is less than said third potential; and means responsive to said control signal and coupled to said signal generating apparatus for inhibiting the generation of said high level signal.

Claim 3

The protection circuit according to claim 1 wherein said means for providing said third potential includes a resistor and a voltage-regulator diode coupled in series combination between said second supply and reference ground.

Claim 4

The protection circuit according to claim 2 wherein said diode has a reverse-breakdown voltage substantially equal to said third potential.

Claim 5

The protection circuit according to claim 1 wherein said comparing means includes a differential-input amplifier.

Claim 6

The protection circuit according to claim 1 wherein said inhibiting means includes a transistor having its gate electrode responsive to said control signal.

Claim 7

In combination: means for generating a high level, controlled risetime, write-erase signal to an electrically erasable programmable read-only memory (E 2 PROM), said signal generating means including means for coupling first and second power supplies thereto, said first and second supplies providing, when operational, first and second potentials, respectively, where said second potential is substantially greater than said first potential, said signal generating means responsive to one voltage level at the input thereof for generating said high level signal and responsive to a different voltage level for providing no output therefrom; means coupled to said second supply for providing a third potential, less than said first potential; and a protection circuit for inhibiting the generation of said high level signal whenever the potential provided from said first supply drops below the level of said third potential while said second supply is operational, said protection circuit including means coupled between said second supply and reference ground for comparing the voltage level of said first supply with said third potential, said comparing means generating a control signal when the voltage level of said first supply is less than said third potential, and means responsive to said control signal and coupled to said signal generating means for inhibiting the generation of said high level signal.

Claim 8

In combination: means for generating a high level, controlled risetime, write-erase signal to an electrically erasable programmable read-only memory (E 2 PROM), said signal generating means including means for coupling first and second power supplies thereto, said first and second supplies providing, when operational, first and second potentials, respectively, where said second potential is substantially greater than said first potential, said signal generating means responsive to one voltage level at the input thereof for generating said high level signal and responsive to a different voltage level for providing no output therefrom; means coupled to said second supply for providing a third potential, less than said first potential; and a protection circuit for inhibiting the generation of said high level signal whenever the potential provided from said first supply drops below the level of said third potential while said second supply is operational, said protection circuit including means coupled between said second supply and reference ground for comparing the voltage level of said first supply with said third potential, said comparing means generating a control signal when the voltage level of said first supply is less than said third potential, and means responsive to said control signal and coupled to said signal generating means for inhibiting the generation of said high level signal.

Claim 9

In combination: an electrically erasable programmable read-only memory (E 2 PROM) having a program voltage terminal which is responsive to a high level, controlled risetime, write-erase signal for enabling changes of data stored by said E 2 PROM; write-erase signal generating means including means for coupling first and second power supplies thereto, said first and second supplies providing, when operational, first and second potentials, respectively, where said second potential is substantially greater than said first potential, said signal generating means responsive to one voltage level at the input thereof for generating said high level signal and responsive to a different voltage level for providing no output therefrom; means coupled to said second supply for providing a third potential, less than said first potential; and a protection circuit for inhibiting the generation of said write-erase signal whenever the potential provided from said first supply drops below the level of said third potential while said second supply is operational, said protection circuit including means coupled between said second supply and reference ground for comparing the voltage level of said first supply with a third potential, less than said first potential, said comparing means generating a control signal when the voltage level of said first supply is less than said third potential, and means responsive to said control signal and coupled to said signal generating means for inhibiting the generation of said high level signal.

Claim 10

In combination: an electrically erasable programmable read-only memory (E 2 PROM) having a program voltage terminal which is responsive to a high level, controlled risetime, write-erase signal for enabling changes of data stored by said E 2 PROM; write-erase signal generating means including means for coupling first and second power supplies thereto, said first and second supplies providing, when operational, first and second potentials, respectively, where said second potential is substantially greater than said first potential, said signal generating means responsive to one voltage level at the input thereof for generating said high level signal and responsive to a different voltage level for providing no output therefrom; means coupled to said second supply for providing a third potential, less than said first potential; and a protection circuit for inhibiting the generation of said write-erase signal whenever the potential provided from said first supply drops below the level of said third potential while said second supply is operational, said protection circuit including means coupled between said second supply and reference ground for comparing the voltage level of said first supply with a third potential, less than said first potential, said comparing means generating a control signal when the voltage level of said first supply is less than said third potential, and means responsive to said control signal and coupled to said signal generating means for inhibiting the generation of said high level signal.