US4366560A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power down detector
Assignee: Motorola Solutions Inc
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Filing: 1980-09-22
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Granted: 1982-12-28
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Expires: 2000-09-22
Abstract
Abstract A circuit for detecting power supply variations in which a first and second transistor are connected in a cross-coupled mode. A load device is connected to each transistor and to a source of power. The loads are unbalanced such that upon application of power to the circuit a first state is always assumed. The cell is forced to its second state. A charge transfer device is connected between first and second nodes formed at the connection between the first transistor and its load and the second transistor and its load. Upon reduction of power supply voltage below that of the active node, a charge transfer takes place which allows the cell to return to its initial state. Detection of the initial state indicates loss or reduction of power has occurred.
Inventors
- 👤 Mark W. McDermott
- 👤 Neil B. Feldman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:03
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/143
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
117 words
A circuit for detecting supply voltage variations thereto comprising, (a) binary means for indicating the circuit to be in a first or second state, (b) means associated with said binary means for causing said binary means to assume a first of said first or second states upon application of a source of power to said circuit, (c) means coupled to said binary means for forcing said binary means to the second of said first or second states, and (d) further means coupled to said binary means and to said source of power for causing said binary means to reassume said first state in the event of reduction of voltage from said source of power to said circuit.
Claim 2
Dependent Claim
117 words
A circuit for detecting supply voltage variations thereto comprising, (a) binary means for indicating the circuit to be in a first or second state, (b) means associated with said binary means for causing said binary means to assume a first of said first or second states upon application of a source of power to said circuit, (c) means coupled to said binary means for forcing said binary means to the second of said first or second states, and (d) further means coupled to said binary means and to said source of power for causing said binary means to reassume said first state in the event of reduction of voltage from said source of power to said circuit.
Claim 3
Dependent Claim
15 words
A circuit as set forth in claim 1 wherein said binary means is a flip-flop.
Claim 4
Dependent Claim
16 words
A circuit as set forth in claim 1 wherein said binary means is a memory cell.
Claim 5
Dependent Claim
18 words
A circuit as set forth in claim 1 wherein said binary means is a pair of cross-coupled transistors.
Claim 6
Dependent Claim
46 words
A circuit as set forth in claim 4 wherein said means for causing said binary means to assume a first state comprises a pair of load devices each connected to one of said pair of cross-coupled transistors, and in said load devices are unequal in gain.
Claim 7
Dependent Claim
45 words
A circuit as set forth in claim 5 wherein the connection of each load to its respective transistor defines a node, and further comprising means connected between said nodes whereby a reduction in voltage from said source of power causes a coupling of said nodes.
Claim 8
Dependent Claim
143 words
A circuit for detecting power variations comprising: (a) a first transistor and a second transistor connected in a cross-coupled configuration; (b) said first transistor having a first load coupled thereto at a first node and to a power supply potential; (c) said second transistor having a second load coupled thereto at a second node and to a power supply potential, said second load having a relatively higher gain than said first load, thereby causing the circuit to assume, upon application of power thereto, a first state; (d) means for applying a signal to said circuit, said signal causing the circuit to assume a second state; (e) a third transistor coupled between said first and second nodes and having an electrode coupled to said power supply potential; (f) whereby a reduction in power supply potential causes the circuit to revert to said first state.
Claim 9
Dependent Claim
143 words
A circuit for detecting power variations comprising: (a) a first transistor and a second transistor connected in a cross-coupled configuration; (b) said first transistor having a first load coupled thereto at a first node and to a power supply potential; (c) said second transistor having a second load coupled thereto at a second node and to a power supply potential, said second load having a relatively higher gain than said first load, thereby causing the circuit to assume, upon application of power thereto, a first state; (d) means for applying a signal to said circuit, said signal causing the circuit to assume a second state; (e) a third transistor coupled between said first and second nodes and having an electrode coupled to said power supply potential; (f) whereby a reduction in power supply potential causes the circuit to revert to said first state.
Claim 10
Dependent Claim
26 words
A circuit as set forth in claim 7 wherein said reversion to said first state is due to charge transfer between said first and second nodes.
Claim 11
Dependent Claim
31 words
A circuit as set forth in claim 7 wherein said first transistor and said second transistor are of a first polarity type and said third transistor is of opposite polarity type.
Claim 12
Dependent Claim
24 words
A circuit as set forth in claim 7 wherein said first load is a passive load and said second load is an active load.
References Cited (Backward Citations)
US3753011A
Cited
US4013902A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-12-27 | 1986-06-28 | 1986-12-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-12-27 | 1990-06-28 | 1990-12-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-12-27 | 1994-06-28 | 1994-12-28 | $7700.00 | Window Closed / Lapsed |