System bus protocol interface circuit

Claim 1

In a computer system having a central control unit and a plurality of peripheral units all being coupled to a common bus, each of said peripheral units being further coupled in parallel to said central control unit by a bus request line through a respectively comprised bus request line terminal for requesting the central control unit for control of said bus and each of said peripheral units being further coupled in series to said central control unit by a bus acknowledgement line to said central control unit through a respectively comprised bus acknowledgement line input terminal for receiving from said central control unit a bus acknowledgement signal granting access to said bus in response to a bus request, and through a respectively comprised bus acknowledgement line output terminal for relaying said received signal to subsequent peripheral units only when it has not requested bus control or when it has initiated an outstanding bus control request and also has finished accessing the bus in response to said received signal, an interface circuit associated with each peripheral unit, respectively for preventing a bus request conflict between said peripheral units, said associated interface circuit respectively comprising: logic means coupled to said bus acknowledgement line input terminal as a respectively associated peripheral unit and to said bus acknowledgement line output terminal of said respectively associated peripheral unit for generating a combinatorial logic output signal responsive to the signals on said bus acknowledgement line input and output terminals, and; latching means coupled in series between said bus request line and said bus request line terminal of said respectively associated peripheral unit, and further connected to the output of said logic means and said bus acknowledgement line output terminal of said respectively associated peripheral unit, for latching itself into a first state in response to a bus request from said respectively associated peripheral unit and for unlatching itself from said first state when the associated peripheral unit has received said but acknowledgement signal if said associated peripheral unit has not initiated any outstanding bus control request, and when the associated peripheral unit has received said bus acknowledgement signal and also has finished accessing said bus in response to said received bus acknowledgement signal if said associated peripheral unit has initiated said outstanding bus control request, (1) the latching into said first state by anyone of said latching means causes all other latching means to be also latched into said first state, (2) a bus request signal is maintained over said bus request line as long as any of said latching means is latched in said first state, (3) said central control unit discontinues said acknowledgement signal over the bus acknowledgement line only when all of said latching means have been respectively unlatched, and (4) in response to said acknowledgement signal from the central control unit, all latching means latched in said first state are sequentially unlatched in corresponding order of the respective time of receipts of said acknowledgement signal by their respectively associated peripheral units.