Patent US4435823A successfully refreshed from Google Patents.
US4435823A
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US
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Adaptive equalizer capable of linear and nonlinear weighting
Assignee: Harris Corp
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Filing: 1980-12-29
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Granted: 1984-03-06
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Expires: 2000-12-29
Abstract
Abstract Equalizers are commonly used in digital data signaling systems to reduce the effects of intersymbol interference on a signal received over a transmission channel. However, conventional equalizers are relatively slow due to their use of multipliers. Also, generally such equalizers are limited to providing a linear response to the received input signal samples. Accordingly, to provide a high-speed equalizer which is capable of both linear and nonlinear response, a transmission channel signal containing intersymbol interference is passed through a delay means which provides sequential Q-bit samples of said transmission channel signal. These Q-bit samples are then applied to a weighting means which includes a memory having stored equalizing weighting values which are accessed in accordance with the Q-bit samples to provide predetermined weighted output words in response to the Q-bit samples. These output words can be either linear or nonlinear with respect to the Q-bit samples. This technique serves to reduce intersymbol interference in the received signal thereby equalizing this signal. Also, since no multipliers are necessary, the equalizing operation can be carried out at a very high speed.
Inventors
- 👤 Robert C. Davis
- 👤 Gautam H. Thaker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 08:13
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03012; H04L25/03019; H04L25/03038; H04L25/03057
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
103 words
An equalizer for reducing intersymbol interference in a signal received over a transmission channel comprising: delay means for receiving said transmission channel signal and providing sequential Q-bit samples of said received transmission channel signal; weighting means comprising a memory coupled to receive the Q-bit samples from said delay means, said memory having stored therein adaptive equalizing weighting values which are accessed in accordance with the Q-bit samples to provide weighted memory output words in response to the received Q-bit sample; and combining means for combining said weighted memory output words accessed from said memory, so as to equalize the received transmission channel signal.
Claim 2
Dependent Claim
103 words
An equalizer for reducing intersymbol interference in a signal received over a transmission channel comprising: delay means for receiving said transmission channel signal and providing sequential Q-bit samples of said received transmission channel signal; weighting means comprising a memory coupled to receive the Q-bit samples from said delay means, said memory having stored therein adaptive equalizing weighting values which are accessed in accordance with the Q-bit samples to provide weighted memory output words in response to the received Q-bit sample; and combining means for combining said weighted memory output words accessed from said memory, so as to equalize the received transmission channel signal.
Claim 3
Dependent Claim
23 words
An equalizer as in claim 1, wherein said memory produces output words which are linearly weighted with respect to the received Q-bit samples.
Claim 4
Dependent Claim
23 words
An equalizer as in claim 1, wherein the memory produces output words which are nonlinearly weighted with respect to the received Q-bit samples.
Claim 5
Dependent Claim
36 words
An equalizer as in claim 1, wherein the delay means comprises an N-stage shift register and wherein the memory comprises a first set of RAM's, wherein individual RAM's are each coupled to individual shift register stages.
Claim 6
Dependent Claim
36 words
An equalizer as in claim 4, wherein said combining means comprises an adder coupled to each RAM output for adding together the respective weighted output word of each RAM to form a composite equalized output signal.
Claim 7
Dependent Claim
45 words
An equalizer as in claim 1, wherein the delay means is an N-stage shift register and wherein the memory and combining means comprises a single adaptive RAM which produces an equalized output signal corresponding to the respective Q-bit output samples of the shift register stages.
Claim 8
Dependent Claim
30 words
An equalizer as in claim 1, further comprising feedback means for updating the equalizing weighting values stored in the memory in accordance with the weighted output words of said memory.
Claim 9
Dependent Claim
36 words
An equalizer as in claim 7, further comprising comparator means for comparing the equalized output signals with an ideal reference signal to produce an error signal for updating the equalizing weighting values stored in the memory.
Claim 10
Dependent Claim
25 words
An equalizer as in claim 8, further comprising means for multiplying said error signal by an update constant k prior to updating of said memory.
Claim 11
Dependent Claim
132 words
An equalizer as in claim 5, further including a recursive loop comprising a second N-stage tapped shift register coupled to receive the composite weighted output signal from said adder, wherein each stage of said second shift register stores a Q-bit sample of said composite weighted output signal, and a second set of RAM's coupled to receive the Q-bit output samples from each stage of said second shift register, said second set of RAM's providing predetermined weighted output words in response to the received second shift register Q-bit output samples, and means for coupling the weighted output words from the second set of RAM's to the adder so that the composite weighted output signal from the adder is a function of the weighted outputs of both the first and second sets of RAM's.
Claim 12
Independent Claim
108 words
A method for equalizing a signal received over a transmission channel to reduce intersymbol interference in said received signal, comprising the steps of: passing said received transmission channel signal through delay means to provide sequential Q-bit samples of said received transmission channel signals; coupling the Q-bit samples to a weighting means comprising a memory having stored adaptive equalizing weighting values and accessing therefrom adaptive equalizing weighting values stored in said memory in accordance with said Q-bit samples, thereby providing weighted output words in response to the received Q-bit samples; and combining said weighted memory output words access from memory, so as to equalize the received transmission channel signal.
Claim 13
Independent Claim
108 words
A method for equalizing a signal received over a transmission channel to reduce intersymbol interference in said received signal, comprising the steps of: passing said received transmission channel signal through delay means to provide sequential Q-bit samples of said received transmission channel signals; coupling the Q-bit samples to a weighting means comprising a memory having stored adaptive equalizing weighting values and accessing therefrom adaptive equalizing weighting values stored in said memory in accordance with said Q-bit samples, thereby providing weighted output words in response to the received Q-bit samples; and combining said weighted memory output words access from memory, so as to equalize the received transmission channel signal.
Claim 14
Dependent Claim
22 words
A method as in claim 11, wherein the memory produces output words which are linearly weighted with respect to the Q-bit samples.
Claim 15
Dependent Claim
22 words
A method as in claim 11, wherein the memory produces output words which are nonlinearly weighted with respect to the Q-bit samples.
Claim 16
Dependent Claim
63 words
A method as in claim 11, wherein the delay means comprises an N-stage shift register and the memory comprises a first set of RAM's, with individual ones of said RAM's being coupled to respective stages of said shift register, and wherein said step of combining includes adding the respective weighted output words of said RAM's together to form a composite equalized output signal.
Claim 17
Dependent Claim
45 words
A method as in claim 11, wherein the delay means comprises an N-stage shift register and the memory comprises a single adaptive RAM for producing an equalized output signal in accordance with the input Q-bit samples received from the respective stages of said shift register.
Claim 18
Dependent Claim
33 words
A method as in claim 11, further comprising the step of feeding back a portion of the equalized output signals of said memory to update the equalizing weighting values stored in said RAM.
Claim 19
Dependent Claim
33 words
A method as in claim 16, further comprising comparing the equalized output signals with an ideal reference signal to produce an error signal for updating the equalizing weighting values stored in said memory.
Claim 20
Dependent Claim
25 words
A method as in claim 17, further comprising multiplying said error signal by an update constant k to produce an updating signal for said memory.
Claim 21
Dependent Claim
116 words
A method as in claim 14, further comprising passing the composite weighted output signal from said adder through a second shift register wherein each stage of said second shift register stores a Q-bit sample of the composite weighted output signal, and coupling the Q-bit samples from said second shift register to a second set of RAM's for accessing predetermined weighted output words in response to the Q-bit output samples from said second shift register, and feeding the weighted output words from said second set of RAM's to the adder so that the composite weighted output signal from said adder is a function of the weighted output signals of both the first and second sets of RAM's.
Claim 22
Dependent Claim
145 words
A high-speed adaptive equalizer for reducing intersymbol interference in a signal received over a transmission channel comprising: an N-stage tapped shift register for receiving said transmission signal and providing sequential Q-bit samples of said received transmission signal; weighting means comprising at least one RAM coupled to receive the Q-bit samples from said shift register, said RAM having stored equalizing weighting values which are accessed in accordance with Q-bit samples to provide a composite equalization signal in response to the received Q-bit samples to thereby equalize the received transmission channel signal; comparator means for comparing said composite equalization signal from said weighting means with an ideal known reference signal to produce an error signal; means for adding the error signal to the equalizing weighting values stored in RAM to produce updated equalizing weighting values; and means for entering the updated equalizing weighting values into the RAM.
Claim 23
Dependent Claim
145 words
A high-speed adaptive equalizer for reducing intersymbol interference in a signal received over a transmission channel comprising: an N-stage tapped shift register for receiving said transmission signal and providing sequential Q-bit samples of said received transmission signal; weighting means comprising at least one RAM coupled to receive the Q-bit samples from said shift register, said RAM having stored equalizing weighting values which are accessed in accordance with Q-bit samples to provide a composite equalization signal in response to the received Q-bit samples to thereby equalize the received transmission channel signal; comparator means for comparing said composite equalization signal from said weighting means with an ideal known reference signal to produce an error signal; means for adding the error signal to the equalizing weighting values stored in RAM to produce updated equalizing weighting values; and means for entering the updated equalizing weighting values into the RAM.
Claim 24
Dependent Claim
28 words
An equalizer as in claim 20, further comprising means coupled between the comparator and the adding means for multiplying the error signal by an update loop constant k.
Claim 25
Independent Claim
145 words
A method for providing high-speed adaptive equalization for reducing intersymbol interference in a signal received over a transmission channel comprising: passing said received transmission channel signal through an N-stage tapped shift register to provide sequential Q-bit samples of said received transmission channel signal; coupling the Q-bit samples to a weighting means comprising at least one RAM having stored therein equalizing weighting values and accessing equalizing weighting values stored in said at least one RAM in accordance with said Q-bit samples, thereby providing a composite equalization signal in response to the received Q-bit samples so as to equalize the received transmission channel signal; comparing said composite equalization signal with an ideal known reference signal to produce an error signal; adding the error signal to equalizing weighting values stored in RAM to produce updated equalizing weighting values; and entering the updated equalizing weighting values in the RAM.
Claim 26
Independent Claim
145 words
A method for providing high-speed adaptive equalization for reducing intersymbol interference in a signal received over a transmission channel comprising: passing said received transmission channel signal through an N-stage tapped shift register to provide sequential Q-bit samples of said received transmission channel signal; coupling the Q-bit samples to a weighting means comprising at least one RAM having stored therein equalizing weighting values and accessing equalizing weighting values stored in said at least one RAM in accordance with said Q-bit samples, thereby providing a composite equalization signal in response to the received Q-bit samples so as to equalize the received transmission channel signal; comparing said composite equalization signal with an ideal known reference signal to produce an error signal; adding the error signal to equalizing weighting values stored in RAM to produce updated equalizing weighting values; and entering the updated equalizing weighting values in the RAM.
Claim 27
Dependent Claim
32 words
A method as in claim 22, further comprising the step of multiplying the error signal by an update loop constant k prior to adding the error signal to the RAM output values.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-03-06 | 1987-09-05 | 1988-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-03-06 | 1991-09-05 | 1992-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-03-06 | 1995-09-05 | 1996-03-06 | $7700.00 | Window Closed / Lapsed |